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https://github.com/AsahiLinux/u-boot
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This adds the clock bindings for Mediatek MT8365 SoC based on the dt-bindings in Linux tag v6.7-rc2. (commit c61978175ac1337f028ac1f956666f16db84f4e5) Signed-off-by: Julien Masson <jmasson@baylibre.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
375 lines
10 KiB
C
375 lines
10 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT8365_H
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#define _DT_BINDINGS_CLK_MT8365_H
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/* TOPCKGEN */
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#define CLK_TOP_CLK_NULL 0
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#define CLK_TOP_I2S0_BCK 1
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#define CLK_TOP_DSI0_LNTC_DSICK 2
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#define CLK_TOP_VPLL_DPIX 3
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#define CLK_TOP_LVDSTX_CLKDIG_CTS 4
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#define CLK_TOP_MFGPLL 5
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#define CLK_TOP_SYSPLL_D2 6
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#define CLK_TOP_SYSPLL1_D2 7
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#define CLK_TOP_SYSPLL1_D4 8
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#define CLK_TOP_SYSPLL1_D8 9
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#define CLK_TOP_SYSPLL1_D16 10
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#define CLK_TOP_SYSPLL_D3 11
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#define CLK_TOP_SYSPLL2_D2 12
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#define CLK_TOP_SYSPLL2_D4 13
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#define CLK_TOP_SYSPLL2_D8 14
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#define CLK_TOP_SYSPLL_D5 15
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#define CLK_TOP_SYSPLL3_D2 16
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#define CLK_TOP_SYSPLL3_D4 17
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#define CLK_TOP_SYSPLL_D7 18
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#define CLK_TOP_SYSPLL4_D2 19
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#define CLK_TOP_SYSPLL4_D4 20
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#define CLK_TOP_UNIVPLL 21
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#define CLK_TOP_UNIVPLL_D2 22
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#define CLK_TOP_UNIVPLL1_D2 23
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#define CLK_TOP_UNIVPLL1_D4 24
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#define CLK_TOP_UNIVPLL_D3 25
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#define CLK_TOP_UNIVPLL2_D2 26
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#define CLK_TOP_UNIVPLL2_D4 27
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#define CLK_TOP_UNIVPLL2_D8 28
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#define CLK_TOP_UNIVPLL2_D32 29
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#define CLK_TOP_UNIVPLL_D5 30
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#define CLK_TOP_UNIVPLL3_D2 31
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#define CLK_TOP_UNIVPLL3_D4 32
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#define CLK_TOP_MMPLL 33
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#define CLK_TOP_MMPLL_D2 34
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#define CLK_TOP_LVDSPLL_D2 35
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#define CLK_TOP_LVDSPLL_D4 36
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#define CLK_TOP_LVDSPLL_D8 37
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#define CLK_TOP_LVDSPLL_D16 38
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#define CLK_TOP_USB20_192M 39
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#define CLK_TOP_USB20_192M_D4 40
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#define CLK_TOP_USB20_192M_D8 41
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#define CLK_TOP_USB20_192M_D16 42
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#define CLK_TOP_USB20_192M_D32 43
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#define CLK_TOP_APLL1 44
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#define CLK_TOP_APLL1_D2 45
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#define CLK_TOP_APLL1_D4 46
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#define CLK_TOP_APLL1_D8 47
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#define CLK_TOP_APLL2 48
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#define CLK_TOP_APLL2_D2 49
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#define CLK_TOP_APLL2_D4 50
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#define CLK_TOP_APLL2_D8 51
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#define CLK_TOP_SYS_26M_D2 52
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#define CLK_TOP_MSDCPLL 53
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#define CLK_TOP_MSDCPLL_D2 54
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#define CLK_TOP_DSPPLL 55
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#define CLK_TOP_DSPPLL_D2 56
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#define CLK_TOP_DSPPLL_D4 57
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#define CLK_TOP_DSPPLL_D8 58
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#define CLK_TOP_APUPLL 59
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#define CLK_TOP_CLK26M_D52 60
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#define CLK_TOP_AXI_SEL 61
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#define CLK_TOP_MEM_SEL 62
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#define CLK_TOP_MM_SEL 63
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#define CLK_TOP_SCP_SEL 64
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#define CLK_TOP_MFG_SEL 65
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#define CLK_TOP_ATB_SEL 66
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#define CLK_TOP_CAMTG_SEL 67
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#define CLK_TOP_CAMTG1_SEL 68
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#define CLK_TOP_UART_SEL 69
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#define CLK_TOP_SPI_SEL 70
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#define CLK_TOP_MSDC50_0_HC_SEL 71
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#define CLK_TOP_MSDC2_2_HC_SEL 72
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#define CLK_TOP_MSDC50_0_SEL 73
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#define CLK_TOP_MSDC50_2_SEL 74
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#define CLK_TOP_MSDC30_1_SEL 75
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#define CLK_TOP_AUDIO_SEL 76
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#define CLK_TOP_AUD_INTBUS_SEL 77
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#define CLK_TOP_AUD_1_SEL 78
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#define CLK_TOP_AUD_2_SEL 79
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#define CLK_TOP_AUD_ENGEN1_SEL 80
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#define CLK_TOP_AUD_ENGEN2_SEL 81
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#define CLK_TOP_AUD_SPDIF_SEL 82
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#define CLK_TOP_DISP_PWM_SEL 83
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#define CLK_TOP_DXCC_SEL 84
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#define CLK_TOP_SSUSB_SYS_SEL 85
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#define CLK_TOP_SSUSB_XHCI_SEL 86
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#define CLK_TOP_SPM_SEL 87
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#define CLK_TOP_I2C_SEL 88
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#define CLK_TOP_PWM_SEL 89
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#define CLK_TOP_SENIF_SEL 90
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#define CLK_TOP_AES_FDE_SEL 91
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#define CLK_TOP_CAMTM_SEL 92
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#define CLK_TOP_DPI0_SEL 93
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#define CLK_TOP_DPI1_SEL 94
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#define CLK_TOP_DSP_SEL 95
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#define CLK_TOP_NFI2X_SEL 96
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#define CLK_TOP_NFIECC_SEL 97
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#define CLK_TOP_ECC_SEL 98
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#define CLK_TOP_ETH_SEL 99
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#define CLK_TOP_GCPU_SEL 100
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#define CLK_TOP_GCPU_CPM_SEL 101
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#define CLK_TOP_APU_SEL 102
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#define CLK_TOP_APU_IF_SEL 103
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#define CLK_TOP_MBIST_DIAG_SEL 104
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#define CLK_TOP_APLL_I2S0_SEL 105
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#define CLK_TOP_APLL_I2S1_SEL 106
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#define CLK_TOP_APLL_I2S2_SEL 107
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#define CLK_TOP_APLL_I2S3_SEL 108
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#define CLK_TOP_APLL_TDMOUT_SEL 109
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#define CLK_TOP_APLL_TDMIN_SEL 110
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#define CLK_TOP_APLL_SPDIF_SEL 111
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#define CLK_TOP_APLL12_CK_DIV0 112
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#define CLK_TOP_APLL12_CK_DIV1 113
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#define CLK_TOP_APLL12_CK_DIV2 114
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#define CLK_TOP_APLL12_CK_DIV3 115
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#define CLK_TOP_APLL12_CK_DIV4 116
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#define CLK_TOP_APLL12_CK_DIV4B 117
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#define CLK_TOP_APLL12_CK_DIV5 118
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#define CLK_TOP_APLL12_CK_DIV5B 119
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#define CLK_TOP_APLL12_CK_DIV6 120
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#define CLK_TOP_AUD_I2S0_M 121
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#define CLK_TOP_AUD_I2S1_M 122
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#define CLK_TOP_AUD_I2S2_M 123
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#define CLK_TOP_AUD_I2S3_M 124
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#define CLK_TOP_AUD_TDMOUT_M 125
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#define CLK_TOP_AUD_TDMOUT_B 126
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#define CLK_TOP_AUD_TDMIN_M 127
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#define CLK_TOP_AUD_TDMIN_B 128
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#define CLK_TOP_AUD_SPDIF_M 129
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#define CLK_TOP_USB20_48M_EN 130
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#define CLK_TOP_UNIVPLL_48M_EN 131
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#define CLK_TOP_LVDSTX_CLKDIG_EN 132
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#define CLK_TOP_VPLL_DPIX_EN 133
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#define CLK_TOP_SSUSB_TOP_CK_EN 134
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#define CLK_TOP_SSUSB_PHY_CK_EN 135
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#define CLK_TOP_CONN_32K 136
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#define CLK_TOP_CONN_26M 137
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#define CLK_TOP_DSP_32K 138
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#define CLK_TOP_DSP_26M 139
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#define CLK_TOP_NR_CLK 140
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#define CLK_TOP_CLK26M 141
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#define CLK_TOP_CLK32K 142
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/* INFRACFG */
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#define CLK_IFR_PMIC_TMR 0
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#define CLK_IFR_PMIC_AP 1
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#define CLK_IFR_PMIC_MD 2
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#define CLK_IFR_PMIC_CONN 3
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#define CLK_IFR_ICUSB 4
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#define CLK_IFR_GCE 5
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#define CLK_IFR_THERM 6
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#define CLK_IFR_PWM_HCLK 7
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#define CLK_IFR_PWM1 8
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#define CLK_IFR_PWM2 9
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#define CLK_IFR_PWM3 10
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#define CLK_IFR_PWM4 11
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#define CLK_IFR_PWM5 12
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#define CLK_IFR_PWM 13
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#define CLK_IFR_UART0 14
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#define CLK_IFR_UART1 15
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#define CLK_IFR_UART2 16
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#define CLK_IFR_DSP_UART 17
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#define CLK_IFR_GCE_26M 18
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#define CLK_IFR_CQ_DMA_FPC 19
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#define CLK_IFR_BTIF 20
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#define CLK_IFR_SPI0 21
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#define CLK_IFR_MSDC0_HCLK 22
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#define CLK_IFR_MSDC2_HCLK 23
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#define CLK_IFR_MSDC1_HCLK 24
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#define CLK_IFR_DVFSRC 25
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#define CLK_IFR_GCPU 26
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#define CLK_IFR_TRNG 27
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#define CLK_IFR_AUXADC 28
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#define CLK_IFR_CPUM 29
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#define CLK_IFR_AUXADC_MD 30
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#define CLK_IFR_AP_DMA 31
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#define CLK_IFR_DEBUGSYS 32
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#define CLK_IFR_AUDIO 33
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#define CLK_IFR_PWM_FBCLK6 34
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#define CLK_IFR_DISP_PWM 35
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#define CLK_IFR_AUD_26M_BK 36
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#define CLK_IFR_CQ_DMA 37
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#define CLK_IFR_MSDC0_SF 38
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#define CLK_IFR_MSDC1_SF 39
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#define CLK_IFR_MSDC2_SF 40
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#define CLK_IFR_AP_MSDC0 41
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#define CLK_IFR_MD_MSDC0 42
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#define CLK_IFR_MSDC0_SRC 43
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#define CLK_IFR_MSDC1_SRC 44
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#define CLK_IFR_MSDC2_SRC 45
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#define CLK_IFR_PWRAP_TMR 46
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#define CLK_IFR_PWRAP_SPI 47
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#define CLK_IFR_PWRAP_SYS 48
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#define CLK_IFR_MCU_PM_BK 49
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#define CLK_IFR_IRRX_26M 50
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#define CLK_IFR_IRRX_32K 51
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#define CLK_IFR_I2C0_AXI 52
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#define CLK_IFR_I2C1_AXI 53
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#define CLK_IFR_I2C2_AXI 54
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#define CLK_IFR_I2C3_AXI 55
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#define CLK_IFR_NIC_AXI 56
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#define CLK_IFR_NIC_SLV_AXI 57
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#define CLK_IFR_APU_AXI 58
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#define CLK_IFR_NFIECC 59
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#define CLK_IFR_NFIECC_BK 60
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#define CLK_IFR_NFI1X_BK 61
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#define CLK_IFR_NFI_BK 62
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#define CLK_IFR_MSDC2_AP_BK 63
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#define CLK_IFR_MSDC2_MD_BK 64
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#define CLK_IFR_MSDC2_BK 65
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#define CLK_IFR_SUSB_133_BK 66
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#define CLK_IFR_SUSB_66_BK 67
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#define CLK_IFR_SSUSB_SYS 68
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#define CLK_IFR_SSUSB_REF 69
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#define CLK_IFR_SSUSB_XHCI 70
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#define CLK_IFR_NR_CLK 71
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/* PERICFG */
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#define CLK_PERIAXI 0
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#define CLK_PERI_NR_CLK 1
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MFGPLL 3
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#define CLK_APMIXED_MSDCPLL 4
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#define CLK_APMIXED_MMPLL 5
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#define CLK_APMIXED_APLL1 6
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#define CLK_APMIXED_APLL2 7
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#define CLK_APMIXED_LVDSPLL 8
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#define CLK_APMIXED_DSPPLL 9
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#define CLK_APMIXED_APUPLL 10
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#define CLK_APMIXED_UNIV_EN 11
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#define CLK_APMIXED_USB20_EN 12
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#define CLK_APMIXED_NR_CLK 13
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/* GCE */
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#define CLK_GCE_FAXI 0
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#define CLK_GCE_NR_CLK 1
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/* AUDIOTOP */
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#define CLK_AUD_AFE 0
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#define CLK_AUD_I2S 1
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#define CLK_AUD_22M 2
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#define CLK_AUD_24M 3
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#define CLK_AUD_INTDIR 4
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#define CLK_AUD_APLL2_TUNER 5
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#define CLK_AUD_APLL_TUNER 6
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#define CLK_AUD_SPDF 7
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#define CLK_AUD_HDMI 8
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#define CLK_AUD_HDMI_IN 9
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#define CLK_AUD_ADC 10
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#define CLK_AUD_DAC 11
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#define CLK_AUD_DAC_PREDIS 12
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#define CLK_AUD_TML 13
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#define CLK_AUD_I2S1_BK 14
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#define CLK_AUD_I2S2_BK 15
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#define CLK_AUD_I2S3_BK 16
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#define CLK_AUD_I2S4_BK 17
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#define CLK_AUD_NR_CLK 18
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/* MIPI_CSI0A */
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#define CLK_MIPI0A_CSR_CSI_EN_0A 0
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#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1
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/* MIPI_CSI0B */
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#define CLK_MIPI0B_CSR_CSI_EN_0B 0
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#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1
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/* MIPI_CSI1A */
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#define CLK_MIPI1A_CSR_CSI_EN_1A 0
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#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1
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/* MIPI_CSI1B */
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#define CLK_MIPI1B_CSR_CSI_EN_1B 0
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#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1
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/* MIPI_CSI2A */
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#define CLK_MIPI2A_CSR_CSI_EN_2A 0
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#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1
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/* MIPI_CSI2B */
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#define CLK_MIPI2B_CSR_CSI_EN_2B 0
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#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1
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/* MCUCFG */
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#define CLK_MCU_BUS_SEL 0
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#define CLK_MCU_NR_CLK 1
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/* MFGCFG */
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#define CLK_MFG_BG3D 0
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#define CLK_MFG_MBIST_DIAG 1
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#define CLK_MFG_NR_CLK 2
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/* MMSYS */
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#define CLK_MM_MM_MDP_RDMA0 0
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#define CLK_MM_MM_MDP_CCORR0 1
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#define CLK_MM_MM_MDP_RSZ0 2
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#define CLK_MM_MM_MDP_RSZ1 3
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#define CLK_MM_MM_MDP_TDSHP0 4
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#define CLK_MM_MM_MDP_WROT0 5
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#define CLK_MM_MM_MDP_WDMA0 6
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#define CLK_MM_MM_DISP_OVL0 7
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#define CLK_MM_MM_DISP_OVL0_2L 8
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#define CLK_MM_MM_DISP_RSZ0 9
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#define CLK_MM_MM_DISP_RDMA0 10
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#define CLK_MM_MM_DISP_WDMA0 11
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#define CLK_MM_MM_DISP_COLOR0 12
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#define CLK_MM_MM_DISP_CCORR0 13
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#define CLK_MM_MM_DISP_AAL0 14
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#define CLK_MM_MM_DISP_GAMMA0 15
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#define CLK_MM_MM_DISP_DITHER0 16
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#define CLK_MM_MM_DSI0 17
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#define CLK_MM_MM_DISP_RDMA1 18
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#define CLK_MM_MM_MDP_RDMA1 19
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#define CLK_MM_DPI0_DPI0 20
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#define CLK_MM_MM_FAKE 21
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#define CLK_MM_MM_SMI_COMMON 22
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#define CLK_MM_MM_SMI_LARB0 23
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#define CLK_MM_MM_SMI_COMM0 24
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#define CLK_MM_MM_SMI_COMM1 25
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#define CLK_MM_MM_CAM_MDP 26
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#define CLK_MM_MM_SMI_IMG 27
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#define CLK_MM_MM_SMI_CAM 28
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#define CLK_MM_IMG_IMG_DL_RELAY 29
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#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30
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#define CLK_MM_DSI0_DIG_DSI 31
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#define CLK_MM_26M_HRTWT 32
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#define CLK_MM_MM_DPI0 33
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#define CLK_MM_LVDSTX_PXL 34
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#define CLK_MM_LVDSTX_CTS 35
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#define CLK_MM_NR_CLK 36
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/* IMGSYS */
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#define CLK_CAM_LARB2 0
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#define CLK_CAM 1
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#define CLK_CAMTG 2
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#define CLK_CAM_SENIF 3
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#define CLK_CAMSV0 4
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#define CLK_CAMSV1 5
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#define CLK_CAM_FDVT 6
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#define CLK_CAM_WPE 7
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#define CLK_CAM_NR_CLK 8
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/* VDECSYS */
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#define CLK_VDEC_VDEC 0
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#define CLK_VDEC_LARB1 1
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#define CLK_VDEC_NR_CLK 2
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/* VENCSYS */
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#define CLK_VENC 0
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#define CLK_VENC_JPGENC 1
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#define CLK_VENC_NR_CLK 2
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/* APUSYS */
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#define CLK_APU_IPU_CK 0
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#define CLK_APU_AXI 1
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#define CLK_APU_JTAG 2
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#define CLK_APU_IF_CK 3
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#define CLK_APU_EDMA 4
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#define CLK_APU_AHB 5
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#define CLK_APU_NR_CLK 6
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#endif /* _DT_BINDINGS_CLK_MT8365_H */
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