mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
0b33770b54
Before this patch you could see in the log: U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:29:27 +0200) PMUFW: v1.1 Loading new PMUFW cfg obj (32 bytes) PMUFW: No permission to change config object Loading new PMUFW cfg obj (2032 bytes) where it is visible that permission is check before sending PMUFW configuration (big size). When this patch is applied it is visible that order is correct. U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:47:08 +0200) Loading new PMUFW cfg obj (2032 bytes) PMUFW: v1.1 Loading new PMUFW cfg obj (32 bytes) Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a0bf4f46d670023da4f848790eece6fff22090c2.1664962765.git.michal.simek@amd.com
667 lines
14 KiB
C
667 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <dfu.h>
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#include <env.h>
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#include <env_internal.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <sata.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <soc.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <wdt.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <zynqmppl.h>
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#include <zynqmp_firmware.h>
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#include <g_dnl.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include "../common/board.h"
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#include "pm_cfg_obj.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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static xilinx_desc zynqmppl = {
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xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
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ZYNQMP_FPGA_FLAGS
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};
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#endif
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int __maybe_unused psu_uboot_init(void)
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{
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int ret;
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ret = psu_init();
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if (ret)
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return ret;
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/*
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* PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
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* supply sense channel to SysMon supply registers inside the IP.
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* This register must be programmed to complete SysMon IP
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* configuration. The default register configuration after
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* power-up is incorrect. Hence, fix this by writing the
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* correct value - 0x3210.
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*/
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writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
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ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
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/* Delay is required for clocks to be propagated */
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udelay(1000000);
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return 0;
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}
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#if !defined(CONFIG_SPL_BUILD)
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# if defined(CONFIG_DEBUG_UART_BOARD_INIT)
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void board_debug_uart_init(void)
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{
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# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
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psu_uboot_init();
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# endif
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}
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# endif
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# if defined(CONFIG_BOARD_EARLY_INIT_F)
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int board_early_init_f(void)
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{
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int ret = 0;
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# if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) && !defined(CONFIG_DEBUG_UART_BOARD_INIT)
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ret = psu_uboot_init();
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# endif
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return ret;
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}
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# endif
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#endif
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static int multi_boot(void)
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{
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u32 multiboot = 0;
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int ret;
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ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
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if (ret)
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return -EINVAL;
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return multiboot;
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}
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#if defined(CONFIG_SPL_BUILD)
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static void restore_jtag(void)
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{
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if (current_el() != 3)
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return;
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writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
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writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
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writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
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writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
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writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
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writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
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}
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#endif
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static void print_secure_boot(void)
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{
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u32 status = 0;
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if (zynqmp_mmio_read((ulong)&csu_base->status, &status))
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return;
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printf("Secure Boot:\t%sauthenticated, %sencrypted\n",
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status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ",
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status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not ");
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}
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int board_init(void)
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{
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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struct udevice *soc;
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char name[SOC_MAX_STR_SIZE];
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int ret;
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/* Check *at build time* if the filename is an non-empty string */
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if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
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zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
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zynqmp_pm_cfg_obj_size);
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#endif
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#if defined(CONFIG_ZYNQMP_FIRMWARE)
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struct udevice *dev;
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uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
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if (!dev)
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panic("PMU Firmware device not found - Enable it");
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#endif
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#if defined(CONFIG_SPL_BUILD)
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printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
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/* the CSU disables the JTAG interface when secure boot is enabled */
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if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
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restore_jtag();
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#else
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if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
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xilinx_read_eeprom();
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#endif
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printf("EL Level:\tEL%d\n", current_el());
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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ret = soc_get(&soc);
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if (!ret) {
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ret = soc_get_machine(soc, name, sizeof(name));
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if (ret >= 0) {
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zynqmppl.name = strdup(name);
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fpga_init();
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fpga_add(fpga_xilinx, &zynqmppl);
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}
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}
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#endif
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/* display secure boot information */
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print_secure_boot();
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if (current_el() == 3)
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printf("Multiboot:\t%d\n", multi_boot());
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() != 3)
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return 0;
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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if (!val) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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return 0;
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}
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unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
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char *const argv[])
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{
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int ret = 0;
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if (current_el() > 1) {
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smp_kick_all_cpus();
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dcache_disable();
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armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
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ES_TO_AARCH64);
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} else {
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printf("FAIL: current EL is not above EL1\n");
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ret = EINVAL;
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}
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return ret;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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#else
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#endif
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#if !CONFIG_IS_ENABLED(SYSRESET)
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void reset_cpu(void)
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{
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}
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#endif
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static u8 __maybe_unused zynqmp_get_bootmode(void)
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{
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u8 bootmode;
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u32 reg = 0;
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int ret;
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ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
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if (ret)
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return -EINVAL;
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debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
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debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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return bootmode;
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}
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#if defined(CONFIG_BOARD_LATE_INIT)
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static const struct {
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u32 bit;
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const char *name;
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} reset_reasons[] = {
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{ RESET_REASON_DEBUG_SYS, "DEBUG" },
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{ RESET_REASON_SOFT, "SOFT" },
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{ RESET_REASON_SRST, "SRST" },
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{ RESET_REASON_PSONLY, "PS-ONLY" },
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{ RESET_REASON_PMU, "PMU" },
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{ RESET_REASON_INTERNAL, "INTERNAL" },
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{ RESET_REASON_EXTERNAL, "EXTERNAL" },
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{}
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};
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static int reset_reason(void)
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{
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u32 reg;
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int i, ret;
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const char *reason = NULL;
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ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
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if (ret)
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return -EINVAL;
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puts("Reset reason:\t");
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for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
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if (reg & reset_reasons[i].bit) {
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reason = reset_reasons[i].name;
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printf("%s ", reset_reasons[i].name);
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break;
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}
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}
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puts("\n");
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env_set("reset_reason", reason);
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return 0;
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}
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static int set_fdtfile(void)
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{
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char *compatible, *fdtfile;
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const char *suffix = ".dtb";
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const char *vendor = "xilinx/";
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int fdt_compat_len;
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if (env_get("fdtfile"))
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return 0;
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compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (compatible && fdt_compat_len) {
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char *name;
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debug("Compatible: %s\n", compatible);
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name = strchr(compatible, ',');
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if (!name)
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return -EINVAL;
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name++;
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fdtfile = calloc(1, strlen(vendor) + strlen(name) +
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strlen(suffix) + 1);
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if (!fdtfile)
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return -ENOMEM;
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sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
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env_set("fdtfile", fdtfile);
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free(fdtfile);
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}
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return 0;
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}
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int board_late_init(void)
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{
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u8 bootmode;
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struct udevice *dev;
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int bootseq = -1;
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int bootseq_len = 0;
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int env_targets_len = 0;
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const char *mode;
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char *new_targets;
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char *env_targets;
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int ret, multiboot;
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#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
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usb_ether_init();
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#endif
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if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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debug("Saved variables - Skipping\n");
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return 0;
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}
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if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
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return 0;
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ret = set_fdtfile();
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if (ret)
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return ret;
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multiboot = multi_boot();
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if (multiboot >= 0)
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env_set_hex("multiboot", multiboot);
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bootmode = zynqmp_get_bootmode();
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puts("Bootmode: ");
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switch (bootmode) {
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case USB_MODE:
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puts("USB_MODE\n");
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mode = "usb_dfu0 usb_dfu1";
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env_set("modeboot", "usb_dfu_spl");
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break;
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case JTAG_MODE:
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puts("JTAG_MODE\n");
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mode = "jtag pxe dhcp";
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env_set("modeboot", "jtagboot");
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break;
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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mode = "qspi0";
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puts("QSPI_MODE\n");
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env_set("modeboot", "qspiboot");
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break;
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case EMMC_MODE:
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puts("EMMC_MODE\n");
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if (uclass_get_device_by_name(UCLASS_MMC,
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"mmc@ff160000", &dev) &&
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uclass_get_device_by_name(UCLASS_MMC,
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"sdhci@ff160000", &dev)) {
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puts("Boot from EMMC but without SD0 enabled!\n");
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return -1;
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}
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debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
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mode = "mmc";
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bootseq = dev_seq(dev);
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env_set("modeboot", "emmcboot");
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break;
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case SD_MODE:
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puts("SD_MODE\n");
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if (uclass_get_device_by_name(UCLASS_MMC,
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"mmc@ff160000", &dev) &&
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uclass_get_device_by_name(UCLASS_MMC,
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"sdhci@ff160000", &dev)) {
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puts("Boot from SD0 but without SD0 enabled!\n");
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return -1;
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}
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debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
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mode = "mmc";
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bootseq = dev_seq(dev);
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env_set("modeboot", "sdboot");
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break;
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case SD1_LSHFT_MODE:
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puts("LVL_SHFT_");
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fallthrough;
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case SD_MODE1:
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puts("SD_MODE1\n");
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if (uclass_get_device_by_name(UCLASS_MMC,
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"mmc@ff170000", &dev) &&
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uclass_get_device_by_name(UCLASS_MMC,
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"sdhci@ff170000", &dev)) {
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puts("Boot from SD1 but without SD1 enabled!\n");
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return -1;
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}
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debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
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mode = "mmc";
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bootseq = dev_seq(dev);
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env_set("modeboot", "sdboot");
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break;
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case NAND_MODE:
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puts("NAND_MODE\n");
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mode = "nand0";
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env_set("modeboot", "nandboot");
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break;
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default:
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mode = "";
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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if (bootseq >= 0) {
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bootseq_len = snprintf(NULL, 0, "%i", bootseq);
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debug("Bootseq len: %x\n", bootseq_len);
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env_set_hex("bootseq", bootseq);
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}
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/*
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* One terminating char + one byte for space between mode
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* and default boot_targets
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*/
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env_targets = env_get("boot_targets");
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if (env_targets)
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
|
|
bootseq_len);
|
|
if (!new_targets)
|
|
return -ENOMEM;
|
|
|
|
if (bootseq >= 0)
|
|
sprintf(new_targets, "%s%x %s", mode, bootseq,
|
|
env_targets ? env_targets : "");
|
|
else
|
|
sprintf(new_targets, "%s %s", mode,
|
|
env_targets ? env_targets : "");
|
|
|
|
env_set("boot_targets", new_targets);
|
|
free(new_targets);
|
|
|
|
reset_reason();
|
|
|
|
return board_late_init_xilinx();
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: Xilinx ZynqMP\n");
|
|
return 0;
|
|
}
|
|
|
|
int mmc_get_env_dev(void)
|
|
{
|
|
struct udevice *dev;
|
|
int bootseq = 0;
|
|
|
|
switch (zynqmp_get_bootmode()) {
|
|
case EMMC_MODE:
|
|
case SD_MODE:
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff160000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff160000", &dev)) {
|
|
return -1;
|
|
}
|
|
bootseq = dev_seq(dev);
|
|
break;
|
|
case SD1_LSHFT_MODE:
|
|
case SD_MODE1:
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff170000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff170000", &dev)) {
|
|
return -1;
|
|
}
|
|
bootseq = dev_seq(dev);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
debug("bootseq %d\n", bootseq);
|
|
|
|
return bootseq;
|
|
}
|
|
|
|
enum env_location env_get_location(enum env_operation op, int prio)
|
|
{
|
|
u32 bootmode = zynqmp_get_bootmode();
|
|
|
|
if (prio)
|
|
return ENVL_UNKNOWN;
|
|
|
|
switch (bootmode) {
|
|
case EMMC_MODE:
|
|
case SD_MODE:
|
|
case SD1_LSHFT_MODE:
|
|
case SD_MODE1:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
|
|
return ENVL_FAT;
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
|
|
return ENVL_EXT4;
|
|
return ENVL_NOWHERE;
|
|
case NAND_MODE:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
|
|
return ENVL_NAND;
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
|
|
return ENVL_UBI;
|
|
return ENVL_NOWHERE;
|
|
case QSPI_MODE_24BIT:
|
|
case QSPI_MODE_32BIT:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
|
|
return ENVL_SPI_FLASH;
|
|
return ENVL_NOWHERE;
|
|
case JTAG_MODE:
|
|
default:
|
|
return ENVL_NOWHERE;
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_SET_DFU_ALT_INFO)
|
|
|
|
#define DFU_ALT_BUF_LEN SZ_1K
|
|
|
|
void set_dfu_alt_info(char *interface, char *devstr)
|
|
{
|
|
int multiboot;
|
|
int bootseq = 0;
|
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
|
|
|
|
if (env_get("dfu_alt_info"))
|
|
return;
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
multiboot = multi_boot();
|
|
if (multiboot < 0)
|
|
multiboot = 0;
|
|
|
|
multiboot = env_get_hex("multiboot", multiboot);
|
|
debug("Multiboot: %d\n", multiboot);
|
|
|
|
switch (zynqmp_get_bootmode()) {
|
|
case EMMC_MODE:
|
|
case SD_MODE:
|
|
case SD1_LSHFT_MODE:
|
|
case SD_MODE1:
|
|
bootseq = mmc_get_env_dev();
|
|
if (!multiboot)
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
"mmc %d=boot.bin fat %d 1;"
|
|
"%s fat %d 1",
|
|
bootseq, bootseq,
|
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
|
|
else
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
"mmc %d=boot%04d.bin fat %d 1;"
|
|
"%s fat %d 1",
|
|
bootseq, multiboot, bootseq,
|
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
|
|
break;
|
|
#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
|
|
case QSPI_MODE_24BIT:
|
|
case QSPI_MODE_32BIT:
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
"sf 0:0=boot.bin raw %x 0x1500000;"
|
|
"%s raw 0x%x 0x500000",
|
|
multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
|
|
CONFIG_SYS_SPI_U_BOOT_OFFS);
|
|
break;
|
|
#endif
|
|
default:
|
|
return;
|
|
}
|
|
|
|
env_set("dfu_alt_info", buf);
|
|
puts("DFU alt info setting: done\n");
|
|
}
|
|
#endif
|