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T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.
T1040QDS board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor
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* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file provides support for the QIXIS of some Freescale reference boards.
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*/
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#ifndef __QIXIS_H_
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#define __QIXIS_H_
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struct qixis {
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u8 id; /* ID value uniquely identifying each QDS board type */
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u8 arch; /* Board version information */
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u8 scver; /* QIXIS Version Register */
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u8 model; /* Information of software programming model version */
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u8 tagdata;
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u8 ctl_sys;
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u8 aux; /* Auxiliary Register,0x06 */
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u8 clk_spd;
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u8 stat_dut;
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u8 stat_sys;
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u8 stat_alrm;
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u8 present;
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u8 present2; /* Presence Status Register 2,0x0c */
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u8 rcw_ctl;
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u8 ctl_led;
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u8 i2cblk;
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u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
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u8 rcfg_st;
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u8 dcm_ad;
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u8 dcm_da;
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u8 dcmd;
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u8 dmsg;
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u8 gdc;
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u8 gdd; /* DCM Debug Data Register,0x17 */
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u8 dmack;
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u8 res1[6];
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u8 watch; /* Watchdog Register,0x1F */
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u8 pwr_ctl[2]; /* Power Control Register,0x20 */
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u8 res2[2];
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u8 pwr_stat[4]; /* Power Status Register,0x24 */
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u8 res3[8];
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u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
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u8 res4[2];
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u8 sclk[3]; /* Clock Configuration Registers,0x34 */
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u8 res5;
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u8 dclk[3];
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u8 res6;
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u8 clk_dspd[3];
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u8 res7;
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u8 rst_ctl; /* Reset Control Register,0x40 */
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u8 rst_stat; /* Reset Status Register */
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u8 rst_rsn; /* Reset Reason Register */
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u8 rst_frc[2]; /* Reset Force Registers,0x43 */
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u8 res8[11];
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u8 brdcfg[16]; /* Board Configuration Register,0x50 */
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u8 dutcfg[16];
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u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
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u8 rcw_data;
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u8 res9[5];
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u8 post_ctl;
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u8 post_stat;
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u8 post_dat[2];
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u8 pi_d[4];
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u8 gpio_io[4];
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u8 gpio_dir[4];
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u8 res10[20];
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u8 rjtag_ctl;
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u8 rjtag_dat;
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u8 res11[2];
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u8 trig_src[4];
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u8 trig_dst[4];
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u8 trig_stat;
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u8 res12[3];
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u8 trig_ctr[4];
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u8 res13[16];
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u8 clk_freq[6]; /* Clock Measurement Registers */
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u8 res_c6[8];
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u8 clk_base[2]; /* Clock Frequency Base Reg */
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u8 res_d0[8];
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u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
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u8 res_c0[6];
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u8 aux2[4]; /* Auxiliary Registers,0xE0 */
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u8 res14[10];
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u8 aux_ad;
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u8 aux_da;
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u8 res15[16];
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};
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u8 qixis_read(unsigned int reg);
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void qixis_write(unsigned int reg, u8 value);
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u16 qixis_read_minor(void);
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char *qixis_read_time(char *result);
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char *qixis_read_tag(char *buf);
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const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
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#ifdef CONFIG_SYS_I2C_FPGA_ADDR
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u8 qixis_read_i2c(unsigned int reg);
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void qixis_write_i2c(unsigned int reg, u8 value);
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#endif
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#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
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#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
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#ifdef CONFIG_SYS_I2C_FPGA_ADDR
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#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
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#define QIXIS_WRITE_I2C(reg, value) \
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qixis_write_i2c(offsetof(struct qixis, reg), value)
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#endif
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#endif
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