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25efd99dbb
Adapt the following patch from spl to nand_spl:
Author: Stefano Babic <sbabic@denx.de>
Date: Thu Dec 15 10:55:37 2011 +0100
nand_spl_simple: store ecc data on the stack
Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing
the fixed address in RAM.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Ilya Yanok <yanok@emcraft.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Simon Schwarz <simonschwarzcor@googlemail.com>
CC: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
While nand_spl is on its way out, in favor of spl, there are still
many boards using it, and conversions are gradual. This allows us
to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
which would otherwise be likely to linger unreferenced after a conversion.
It also eliminates a temporary error in the hawkboard_nand build, since
the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
the spl conversion is pending (and may be merged via a different tree).
Signed-off-by: Scott Wood <scottwood@freescale.com>
309 lines
9.7 KiB
C
309 lines
9.7 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Gary Jennejohn <garyj@denx.de>
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* David Mueller <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
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#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
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#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
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#define CONFIG_PERIPORT_REMAP
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#define CONFIG_PERIPORT_BASE 0x70000000
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#define CONFIG_PERIPORT_SIZE 0x13
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#define CONFIG_SYS_IRAM_BASE 0x0c000000 /* Internal SRAM base address */
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#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */
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#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_SDRAM_BASE 0x50000000
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/* input clock of PLL: SMDK6400 has 12MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 12000000
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#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
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#define CONFIG_ENABLE_MMU
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#endif
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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/*
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* Architecture magic and machine type
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*/
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#define CONFIG_MACH_TYPE 1270
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_CS8900 /* we have a CS8900 on-board */
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#define CONFIG_CS8900_BASE 0x18800300
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#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#define CONFIG_CMDLINE_EDITING
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_NAND
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#if defined(CONFIG_BOOT_ONENAND)
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#define CONFIG_CMD_ONENAND
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#endif
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
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#define CONFIG_SYS_HZ 1000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
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/**********************************
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Support Clock Settings
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**********************************
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Setting SYNC ASYNC
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----------------------------------
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667_133_66 X O
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533_133_66 O O
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400_133_66 X O
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400_100_50 O O
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**********************************/
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/*#define CONFIG_CLK_667_133_66*/
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#define CONFIG_CLK_533_133_66
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/*
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#define CONFIG_CLK_400_100_50
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#define CONFIG_CLK_400_133_66
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#define CONFIG_SYNC_MODE
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*/
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/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
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#define CONFIG_SYS_FLASH_BASE 0x10000000
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
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#define CONFIG_SYS_MAX_FLASH_SECT 40
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#define CONFIG_AMD_LV800
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#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
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/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_FLASH_CFI_LEGACY
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#define CONFIG_SYS_FLASH_LEGACY_512Kx16
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/*
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* SMDK6400 board specific data
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*/
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#define CONFIG_IDENT_STRING " for SMDK6400"
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/* base address for uboot */
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#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
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/* total memory available to uboot */
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#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
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/* Put environment copies after the end of U-Boot owned RAM */
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#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
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#ifdef CONFIG_ENABLE_MMU
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#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
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#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
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"bootm 0xc0018000"
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#else
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#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
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#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
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"bootm 0x50018000"
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#endif
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/* NAND U-Boot load and start address */
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#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
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#define CONFIG_ENV_OFFSET 0x0040000
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/* NAND configuration */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x70200010
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#define CONFIG_SYS_S3C_NAND_HWECC
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#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
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#define CONFIG_SYS_NAND_WP 1
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#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
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#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
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/* NAND chip page size */
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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/* NAND chip block size */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/* NAND chip page per block count */
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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/* Location of the bad-block label */
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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/* Extra address cycle for > 128MiB */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
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#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
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/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
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#define CONFIG_SYS_NAND_ECCBYTES 4
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/* Size of a single OOB region */
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#define CONFIG_SYS_NAND_OOBSIZE 64
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/* ECC byte positions */
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#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63}
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/* Boot configuration (define only one of next 3) */
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#define CONFIG_BOOT_NAND
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/* None of these are currently implemented. Left from the original Samsung
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* version for reference
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#define CONFIG_BOOT_NOR
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#define CONFIG_BOOT_MOVINAND
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#define CONFIG_BOOT_ONENAND
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*/
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#define CONFIG_NAND
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#define CONFIG_NAND_S3C64XX
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/* Unimplemented or unsupported. See comment above.
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#define CONFIG_ONENAND
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#define CONFIG_MOVINAND
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*/
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/* Settings as above boot configuration */
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_BOOTARGS "console=ttySAC,115200"
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#if !defined(CONFIG_ENABLE_MMU)
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#define CONFIG_CMD_USB 1
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#define CONFIG_USB_S3C64XX
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_USB_STORAGE 1
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#endif
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#define CONFIG_DOS_PARTITION 1
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
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# error "usb_ohci.c is currently broken with MMU enabled."
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#endif
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#endif /* __CONFIG_H */
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