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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
346 lines
7.9 KiB
C
346 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/stm32.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#define STM32_GPIOS_PER_BANK 16
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#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
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#define MODE_BITS_MASK 3
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#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
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#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
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#define PUPD_MASK 3
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#define OTYPE_BITS(gpio_pin) (gpio_pin)
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#define OTYPE_MSK 1
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static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
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int idx,
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int mode)
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{
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int bits_index;
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int mask;
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bits_index = MODE_BITS(idx);
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mask = MODE_BITS_MASK << bits_index;
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clrsetbits_le32(®s->moder, mask, mode << bits_index);
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}
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static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
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{
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return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
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}
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static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
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int idx,
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enum stm32_gpio_otype otype)
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{
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int bits;
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bits = OTYPE_BITS(idx);
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clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
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}
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static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
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int idx)
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{
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return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
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}
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static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
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int idx,
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enum stm32_gpio_pupd pupd)
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{
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int bits;
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bits = PUPD_BITS(idx);
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clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
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}
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static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
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int idx)
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{
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return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
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}
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/*
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* convert gpio offset to gpio index taking into account gpio holes
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* into gpio bank
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*/
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int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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unsigned int idx = 0;
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int i;
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for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
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if (priv->gpio_range & BIT(i)) {
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if (idx == offset)
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return idx;
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idx++;
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}
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}
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/* shouldn't happen */
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return -EINVAL;
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}
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static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
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return 0;
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}
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static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
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writel(BSRR_BIT(idx, value), ®s->bsrr);
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return 0;
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}
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static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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return readl(®s->idr) & BIT(idx) ? 1 : 0;
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}
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static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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writel(BSRR_BIT(idx, value), ®s->bsrr);
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return 0;
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}
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static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int bits_index;
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int mask;
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int idx;
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u32 mode;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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bits_index = MODE_BITS(idx);
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mask = MODE_BITS_MASK << bits_index;
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mode = (readl(®s->moder) & mask) >> bits_index;
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if (mode == STM32_GPIO_MODE_OUT)
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return GPIOF_OUTPUT;
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if (mode == STM32_GPIO_MODE_IN)
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return GPIOF_INPUT;
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if (mode == STM32_GPIO_MODE_AN)
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return GPIOF_UNUSED;
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return GPIOF_FUNC;
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}
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static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
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ulong flags)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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if (flags & GPIOD_IS_OUT) {
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int value = GPIOD_FLAGS_OUTPUT(flags);
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if (flags & GPIOD_OPEN_DRAIN)
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stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
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else
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stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
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stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
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writel(BSRR_BIT(idx, value), ®s->bsrr);
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} else if (flags & GPIOD_IS_IN) {
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stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
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}
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if (flags & GPIOD_PULL_UP)
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stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
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else if (flags & GPIOD_PULL_DOWN)
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stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
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return 0;
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}
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static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
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ulong *flags)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct stm32_gpio_regs *regs = priv->regs;
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int idx;
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ulong dir_flags = 0;
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idx = stm32_offset_to_index(dev, offset);
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if (idx < 0)
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return idx;
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switch (stm32_gpio_get_moder(regs, idx)) {
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case STM32_GPIO_MODE_OUT:
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dir_flags |= GPIOD_IS_OUT;
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if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
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dir_flags |= GPIOD_OPEN_DRAIN;
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if (readl(®s->idr) & BIT(idx))
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dir_flags |= GPIOD_IS_OUT_ACTIVE;
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break;
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case STM32_GPIO_MODE_IN:
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dir_flags |= GPIOD_IS_IN;
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break;
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default:
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break;
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}
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switch (stm32_gpio_get_pupd(regs, idx)) {
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case STM32_GPIO_PUPD_UP:
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dir_flags |= GPIOD_PULL_UP;
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break;
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case STM32_GPIO_PUPD_DOWN:
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dir_flags |= GPIOD_PULL_DOWN;
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break;
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default:
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break;
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}
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*flags = dir_flags;
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return 0;
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}
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static const struct dm_gpio_ops gpio_stm32_ops = {
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.direction_input = stm32_gpio_direction_input,
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.direction_output = stm32_gpio_direction_output,
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.get_value = stm32_gpio_get_value,
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.set_value = stm32_gpio_set_value,
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.get_function = stm32_gpio_get_function,
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.set_dir_flags = stm32_gpio_set_dir_flags,
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.get_dir_flags = stm32_gpio_get_dir_flags,
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};
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static int gpio_stm32_probe(struct udevice *dev)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ofnode_phandle_args args;
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const char *name;
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struct clk clk;
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fdt_addr_t addr;
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int ret, i;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = (struct stm32_gpio_regs *)addr;
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name = dev_read_string(dev, "st,bank-name");
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if (!name)
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return -EINVAL;
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uc_priv->bank_name = name;
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i = 0;
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ret = dev_read_phandle_with_args(dev, "gpio-ranges",
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NULL, 3, i, &args);
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if (!ret && args.args_count < 3)
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return -EINVAL;
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if (ret == -ENOENT) {
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uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
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priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
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}
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while (ret != -ENOENT) {
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priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
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args.args[0]);
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uc_priv->gpio_count += args.args[2];
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ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
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++i, &args);
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if (!ret && args.args_count < 3)
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return -EINVAL;
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}
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dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
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(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
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priv->gpio_range);
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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debug("clock enabled for device %s\n", dev->name);
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return 0;
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}
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U_BOOT_DRIVER(gpio_stm32) = {
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.name = "gpio_stm32",
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.id = UCLASS_GPIO,
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.probe = gpio_stm32_probe,
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.ops = &gpio_stm32_ops,
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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.priv_auto = sizeof(struct stm32_gpio_priv),
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};
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