mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
cbff9f80ce
Synchronize DTs with mainline Linux 4.19.6 , commit 96db90800c06d3fe3fa08eb6222fe201286bb778 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- V2: Rebase on u-boot/master
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
|
*/
|
|
#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
|
|
#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
|
|
|
|
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
|
|
|
/* r8a77965 CPG Core Clocks */
|
|
#define R8A77965_CLK_Z 0
|
|
#define R8A77965_CLK_ZR 1
|
|
#define R8A77965_CLK_ZG 2
|
|
#define R8A77965_CLK_ZTR 3
|
|
#define R8A77965_CLK_ZTRD2 4
|
|
#define R8A77965_CLK_ZT 5
|
|
#define R8A77965_CLK_ZX 6
|
|
#define R8A77965_CLK_S0D1 7
|
|
#define R8A77965_CLK_S0D2 8
|
|
#define R8A77965_CLK_S0D3 9
|
|
#define R8A77965_CLK_S0D4 10
|
|
#define R8A77965_CLK_S0D6 11
|
|
#define R8A77965_CLK_S0D8 12
|
|
#define R8A77965_CLK_S0D12 13
|
|
#define R8A77965_CLK_S1D1 14
|
|
#define R8A77965_CLK_S1D2 15
|
|
#define R8A77965_CLK_S1D4 16
|
|
#define R8A77965_CLK_S2D1 17
|
|
#define R8A77965_CLK_S2D2 18
|
|
#define R8A77965_CLK_S2D4 19
|
|
#define R8A77965_CLK_S3D1 20
|
|
#define R8A77965_CLK_S3D2 21
|
|
#define R8A77965_CLK_S3D4 22
|
|
#define R8A77965_CLK_LB 23
|
|
#define R8A77965_CLK_CL 24
|
|
#define R8A77965_CLK_ZB3 25
|
|
#define R8A77965_CLK_ZB3D2 26
|
|
#define R8A77965_CLK_CR 27
|
|
#define R8A77965_CLK_CRD2 28
|
|
#define R8A77965_CLK_SD0H 29
|
|
#define R8A77965_CLK_SD0 30
|
|
#define R8A77965_CLK_SD1H 31
|
|
#define R8A77965_CLK_SD1 32
|
|
#define R8A77965_CLK_SD2H 33
|
|
#define R8A77965_CLK_SD2 34
|
|
#define R8A77965_CLK_SD3H 35
|
|
#define R8A77965_CLK_SD3 36
|
|
#define R8A77965_CLK_SSP2 37
|
|
#define R8A77965_CLK_SSP1 38
|
|
#define R8A77965_CLK_SSPRS 39
|
|
#define R8A77965_CLK_RPC 40
|
|
#define R8A77965_CLK_RPCD2 41
|
|
#define R8A77965_CLK_MSO 42
|
|
#define R8A77965_CLK_CANFD 43
|
|
#define R8A77965_CLK_HDMI 44
|
|
#define R8A77965_CLK_CSI0 45
|
|
#define R8A77965_CLK_CP 46
|
|
#define R8A77965_CLK_CPEX 47
|
|
#define R8A77965_CLK_R 48
|
|
#define R8A77965_CLK_OSC 49
|
|
|
|
#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
|