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db75356f14
The bcm2835 and bcm2836 are essentially identical, except: - The CPU is an ARM1176 v.s. a quad-core Cortex-A7. - The physical address of many IO controllers has moved. Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH), update the existing bcm2835 code to handle the minor differences, and plumb it into the ARMv7 CPU architecture. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
/*
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* Copyright (C) 2012 Vikram Narayananan
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* <vikram186@gmail.com>
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* (C) Copyright 2012,2015 Stephen Warren
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BCM2835_GPIO_H_
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#define _BCM2835_GPIO_H_
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#ifdef CONFIG_BCM2836
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#define BCM2835_GPIO_BASE 0x3f200000
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#else
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#define BCM2835_GPIO_BASE 0x20200000
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#endif
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#define BCM2835_GPIO_COUNT 54
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#define BCM2835_GPIO_FSEL_MASK 0x7
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#define BCM2835_GPIO_INPUT 0x0
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#define BCM2835_GPIO_OUTPUT 0x1
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#define BCM2835_GPIO_ALT0 0x4
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#define BCM2835_GPIO_ALT1 0x5
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#define BCM2835_GPIO_ALT2 0x6
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#define BCM2835_GPIO_ALT3 0x7
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#define BCM2835_GPIO_ALT4 0x3
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#define BCM2835_GPIO_ALT5 0x2
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#define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1)
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#define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f)
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#define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10)
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#define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3)
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struct bcm2835_gpio_regs {
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u32 gpfsel[6];
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u32 reserved1;
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u32 gpset[2];
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u32 reserved2;
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u32 gpclr[2];
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u32 reserved3;
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u32 gplev[2];
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u32 reserved4;
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u32 gpeds[2];
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u32 reserved5;
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u32 gpren[2];
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u32 reserved6;
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u32 gpfen[2];
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u32 reserved7;
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u32 gphen[2];
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u32 reserved8;
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u32 gplen[2];
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u32 reserved9;
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u32 gparen[2];
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u32 reserved10;
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u32 gppud;
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u32 gppudclk[2];
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};
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/**
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* struct bcm2835_gpio_platdata - GPIO platform description
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*
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* @base: Base address of GPIO controller
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*/
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struct bcm2835_gpio_platdata {
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unsigned long base;
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};
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#endif /* _BCM2835_GPIO_H_ */
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