mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-15 07:43:07 +00:00
8c103c33fb
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
283 lines
8 KiB
Text
283 lines
8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am642.dtsi"
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#include "k3-am64-evm-ddr4-1600MTs.dtsi"
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#include "k3-am64-ddr.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a53_0;
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};
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memory@80000000 {
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device_type = "memory";
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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bootph-pre-ram;
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};
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a53_0: a53@0 {
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compatible = "ti,am654-rproc";
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reg = <0x00 0x00a90000 0x00 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 135 0>;
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clocks = <&k3_clks 61 0>;
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assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
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assigned-clock-parents = <&k3_clks 61 2>;
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assigned-clock-rates = <200000000>, <1000000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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bootph-pre-ram;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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clk_200mhz: dummy-clock-200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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bootph-pre-ram;
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};
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vtt_supply: vtt-supply {
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compatible = "regulator-gpio";
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regulator-name = "vtt";
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regulator-min-microvolt = <0>;
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regulator-max-microvolt = <3300000>;
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gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
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states = <0 0x0 3300000 0x1>;
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bootph-pre-ram;
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};
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};
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&cbass_main {
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sysctrler: sysctrler {
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compatible = "ti,am654-system-controller";
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mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
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mbox-names = "tx", "rx";
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bootph-pre-ram;
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};
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};
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&cbass_main {
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main_esm: esm@420000 {
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compatible = "ti,j721e-esm";
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reg = <0x0 0x420000 0x0 0x1000>;
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ti,esm-pins = <160>, <161>;
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bootph-pre-ram;
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};
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};
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&cbass_mcu {
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bootph-pre-ram;
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mcu_esm: esm@4100000 {
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compatible = "ti,j721e-esm";
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reg = <0x0 0x4100000 0x0 0x1000>;
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ti,esm-pins = <0>, <1>;
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bootph-pre-ram;
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};
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};
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&main_pmx0 {
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bootph-pre-ram;
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main_uart0_pins_default: main-uart0-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
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AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
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AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
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AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
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>;
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};
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main_uart1_pins_default: main-uart1-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
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AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
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AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
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AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
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>;
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};
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main_mmc0_pins_default: main-mmc0-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
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AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
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AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
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AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
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AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
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AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
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AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
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AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
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>;
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};
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ddr_vtt_pins_default: ddr-vtt-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
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>;
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};
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main_usb0_pins_default: main-usb0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
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>;
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};
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mdio1_pins_default: mdio1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
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>;
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};
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rgmii1_pins_default: rgmii1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
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AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
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AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
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AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
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AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
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AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
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AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
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AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
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AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
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AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
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AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
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AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
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>;
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};
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rgmii2_pins_default: rgmii2-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
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AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
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AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
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AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
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AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
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AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
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AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
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AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
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AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
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AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
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AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
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>;
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};
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};
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&dmsc {
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mboxes= <&secure_proxy_main 0>,
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<&secure_proxy_main 1>,
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<&secure_proxy_main 0>;
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mbox-names = "rx", "tx", "notify";
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ti,host-id = <35>;
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ti,secure-host;
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};
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&main_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&main_uart1 {
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bootph-pre-ram;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart1_pins_default>;
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};
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&memorycontroller {
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vtt-supply = <&vtt_supply>;
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pinctrl-names = "default";
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pinctrl-0 = <&ddr_vtt_pins_default>;
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};
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&sdhci0 {
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/delete-property/ power-domains;
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clocks = <&clk_200mhz>;
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clock-names = "clk_xin";
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ti,driver-strength-ohm = <50>;
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disable-wp;
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pinctrl-0 = <&main_mmc0_pins_default>;
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};
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&sdhci1 {
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/delete-property/ power-domains;
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clocks = <&clk_200mhz>;
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clock-names = "clk_xin";
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ti,driver-strength-ohm = <50>;
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disable-wp;
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pinctrl-0 = <&main_mmc1_pins_default>;
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};
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&main_gpio0 {
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bootph-pre-ram;
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/delete-property/ power-domains;
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};
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/* EEPROM might be read before SYSFW is available */
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&main_i2c0 {
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/delete-property/ power-domains;
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};
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&usbss0 {
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ti,vbus-divider;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "otg";
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maximum-speed = "high-speed";
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pinctrl-names = "default";
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pinctrl-0 = <&main_usb0_pins_default>;
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};
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#include "k3-am642-evm-u-boot.dtsi"
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