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840f8923a0
Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling ET1011C gigabit phy. which overrides get_link_speed function from default implementation. This enables output of 125 MHz reference clock on SYS_CLK pin. Signed-off-by: Prakash PM <prakash.pm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/*
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* LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <net.h>
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#include <miiphy.h>
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#include <asm/arch/emac_defs.h>
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#ifdef CONFIG_DRIVER_TI_EMAC
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#ifdef CONFIG_CMD_NET
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/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
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#define MII_PHY_CONFIG_REG 22
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/* PHY Config bits */
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#define PHY_SYS_CLK_EN (1 << 4)
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int et1011c_get_link_speed(int phy_addr)
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{
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u_int16_t data;
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if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
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davinci_eth_phy_read(EMAC_MDIO_PHY_NUM,
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MII_PHY_CONFIG_REG, &data);
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/* Enable 125MHz clock sourced from PHY */
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davinci_eth_phy_write(EMAC_MDIO_PHY_NUM,
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MII_PHY_CONFIG_REG,
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data | PHY_SYS_CLK_EN);
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return (1);
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}
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return (0);
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* CONFIG_DRIVER_ETHER */
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