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addb2e1650
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is implemented for these boards.
868 lines
30 KiB
C
868 lines
30 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap2420.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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#include <asm/arch/mem.h>
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#include <i2c.h>
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#include <asm/mach-types.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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#endif
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void wait_for_command_complete(unsigned int wd_base);
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/*******************************************************
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* Routine: delay
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* Description: spinning delay to use before udelay works
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******************************************************/
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static inline void delay (unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*****************************************
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* Routine: board_init
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* Description: Early hardware init.
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*****************************************/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gpmc_init(); /* in SRAM or SDRM, finish GPMC */
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
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gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
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return 0;
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}
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/**********************************************************
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* Routine: try_unlock_sram()
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* Description: If chip is GP type, unlock the SRAM for
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* general use.
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***********************************************************/
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void try_unlock_sram(void)
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{
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/* if GP device unlock device SRAM for general use */
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if (get_device_type() == GP_DEVICE) {
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__raw_writel(0xFF, A_REQINFOPERM0);
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__raw_writel(0xCFDE, A_READPERM0);
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__raw_writel(0xCFDE, A_WRITEPERM0);
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}
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}
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/**********************************************************
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* Routine: s_init
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* Description: Does early system init of muxing and clocks.
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* - Called path is with sram stack.
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**********************************************************/
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void s_init(void)
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{
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int in_sdram = running_in_sdram();
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watchdog_init();
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set_muxconf_regs();
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delay(100);
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try_unlock_sram();
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if(!in_sdram)
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prcm_init();
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peripheral_enable();
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icache_enable();
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if (!in_sdram)
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sdrc_init();
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}
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/*******************************************************
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* Routine: misc_init_r
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* Description: Init ethernet (done here so udelay works)
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********************************************************/
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int misc_init_r (void)
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{
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ether_init(); /* better done here so timers are init'ed */
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return(0);
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}
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/****************************************
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*****************************************/
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void watchdog_init(void)
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{
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/* There are 4 watch dogs. 1 secure, and 3 general purpose.
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* The ROM takes care of the secure one. Of the 3 GP ones,
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* 1 can reset us directly, the other 2 only generate MPU interrupts.
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*/
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__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
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wait_for_command_complete(WD2_BASE);
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__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
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#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
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__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
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wait_for_command_complete(WD3_BASE);
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__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
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__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
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wait_for_command_complete(WD4_BASE);
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__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
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#endif
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}
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/******************************************************
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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******************************************************/
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void wait_for_command_complete(unsigned int wd_base)
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{
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int pending = 1;
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do {
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pending = __raw_readl(wd_base+WWPS);
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} while (pending);
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}
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/*******************************************************************
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* Routine:ether_init
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* Description: take the Ethernet controller out of reset and wait
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* for the EEPROM load to complete.
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******************************************************************/
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void ether_init (void)
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{
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#ifdef CONFIG_DRIVER_LAN91C96
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int cnt = 20;
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__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
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__raw_writew(0x0, LAN_RESET_REGISTER);
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do {
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__raw_writew(0x1, LAN_RESET_REGISTER);
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udelay (100);
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if (cnt == 0)
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goto h4reset_err_out;
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--cnt;
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} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
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cnt = 20;
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do {
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__raw_writew(0x0, LAN_RESET_REGISTER);
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udelay (100);
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if (cnt == 0)
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goto h4reset_err_out;
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--cnt;
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} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
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udelay (1000);
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*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
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udelay (1000);
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h4reset_err_out:
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return;
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#endif
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}
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/**********************************************
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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**********************************************/
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int size0=0,size1=0;
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u32 mtype, btype, rev, cpu;
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u8 chg_on = 0x5; /* enable charge of back up battery */
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u8 vmode_on = 0x8C;
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#define NOT_EARLY 0
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
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btype = get_board_type();
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mtype = get_mem_type();
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rev = get_cpu_rev();
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cpu = get_cpu_type();
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display_board_info(btype);
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if (btype == BOARD_H4_MENELAUS){
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update_mux(btype,mtype); /* combo part on menelaus */
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i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
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i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
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}
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if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
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do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
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}
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size0 = get_sdr_cs_size(SDRC_CS0_OSET);
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size1 = get_sdr_cs_size(SDRC_CS1_OSET);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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else /* ES2 and above can remap at 32MB granularity */
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
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gd->bd->bi_dram[1].size = size1;
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return 0;
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}
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/**********************************************************
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers
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* specific to the hardware
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*********************************************************/
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void set_muxconf_regs (void)
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{
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muxSetupSDRC();
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muxSetupGPMC();
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muxSetupUsb0();
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muxSetupUart3();
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muxSetupI2C1();
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muxSetupUART1();
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muxSetupLCD();
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muxSetupCamera();
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muxSetupMMCSD();
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muxSetupTouchScreen();
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muxSetupHDQ();
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}
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/*****************************************************************
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* Routine: peripheral_enable
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* Description: Enable the clks & power for perifs (GPT2, UART1,...)
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******************************************************************/
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void peripheral_enable(void)
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{
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unsigned int v, if_clks=0, func_clks=0;
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/* Enable GP2 timer.*/
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if_clks |= BIT4;
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func_clks |= BIT4;
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v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
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__raw_writel(v, CM_CLKSEL2_CORE);
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__raw_writel(0x1, CM_CLKSEL_WKUP);
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#ifdef CFG_NS16550
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/* Enable UART1 clock */
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func_clks |= BIT21;
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if_clks |= BIT21;
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#endif
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v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
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__raw_writel(v,CM_ICLKEN1_CORE );
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v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
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__raw_writel(v, CM_FCLKEN1_CORE);
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delay(1000);
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#ifndef KERNEL_UPDATED
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{
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#define V1 0xffffffff
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#define V2 0x00000007
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__raw_writel(V1, CM_FCLKEN1_CORE);
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__raw_writel(V2, CM_FCLKEN2_CORE);
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__raw_writel(V1, CM_ICLKEN1_CORE);
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__raw_writel(V1, CM_ICLKEN2_CORE);
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}
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#endif
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}
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/****************************************
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* Routine: muxSetupUsb0 (ostboot)
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* Description: Setup usb muxing
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*****************************************/
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void muxSetupUsb0(void)
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{
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volatile uint8 *MuxConfigReg;
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volatile uint32 *otgCtrlReg;
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
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*MuxConfigReg &= (uint8)(~0x1F);
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/* setup for USB VBus detection */
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otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
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*otgCtrlReg |= 0x00040000; /* bit 18 */
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}
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/****************************************
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* Routine: muxSetupUart3 (ostboot)
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* Description: Setup uart3 muxing
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*****************************************/
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void muxSetupUart3(void)
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{
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volatile uint8 *MuxConfigReg;
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
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*MuxConfigReg &= (uint8)(~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
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*MuxConfigReg &= (uint8)(~0x1F);
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}
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/****************************************
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* Routine: muxSetupI2C1 (ostboot)
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* Description: Setup i2c muxing
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*****************************************/
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void muxSetupI2C1(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* I2C1 Clock pin configuration, PIN = M19 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* I2C1 Data pin configuration, PIN = L15 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* Pull-up required on data line */
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/* external pull-up already present. */
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/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
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}
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/****************************************
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* Routine: muxSetupUART1 (ostboot)
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* Description: Set up uart1 muxing
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*****************************************/
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void muxSetupUART1(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* UART1_CTS pin configuration, PIN = D21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* UART1_RTS pin configuration, PIN = H21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* UART1_TX pin configuration, PIN = L20 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* UART1_RX pin configuration, PIN = T21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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}
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/****************************************
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* Routine: muxSetupLCD (ostboot)
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* Description: Setup lcd muxing
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*****************************************/
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void muxSetupLCD(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* LCD_D0 pin configuration, PIN = Y7 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D1 pin configuration, PIN = P10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D2 pin configuration, PIN = V8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D3 pin configuration, PIN = Y8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D4 pin configuration, PIN = W8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D5 pin configuration, PIN = R10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D6 pin configuration, PIN = Y9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D7 pin configuration, PIN = V9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D8 pin configuration, PIN = W9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D9 pin configuration, PIN = P11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D10 pin configuration, PIN = V10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D11 pin configuration, PIN = Y10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D12 pin configuration, PIN = W10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D13 pin configuration, PIN = R11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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/* LCD_D14 pin configuration, PIN = V11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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|
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/* LCD_D15 pin configuration, PIN = W11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
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|
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/* LCD_D16 pin configuration, PIN = P12 */
|
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
|
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*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* LCD_D17 pin configuration, PIN = R12 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* LCD_PCLK pin configuration, PIN = W6 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* LCD_VSYNC pin configuration, PIN = V7 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* LCD_HSYNC pin configuration, PIN = Y6 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* LCD_ACBIAS pin configuration, PIN = W7 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
}
|
|
|
|
/****************************************
|
|
* Routine: muxSetupCamera (ostboot)
|
|
* Description: Setup camera muxing
|
|
*****************************************/
|
|
void muxSetupCamera(void)
|
|
{
|
|
volatile unsigned char *MuxConfigReg;
|
|
|
|
/* CAMERA_RSTZ pin configuration, PIN = Y16 */
|
|
/* CAM_RST is connected through the I2C IO expander.*/
|
|
/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
|
|
/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_XCLK pin configuration, PIN = U3 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_LCLK pin configuration, PIN = V5 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_VSYNC pin configuration, PIN = U2 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_HSYNC pin configuration, PIN = T3 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT0 pin configuration, PIN = T4 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT1 pin configuration, PIN = V2 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT2 pin configuration, PIN = V3 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT3 pin configuration, PIN = U4 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT4 pin configuration, PIN = W2 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT5 pin configuration, PIN = V4 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT6 pin configuration, PIN = W3 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT7 pin configuration, PIN = Y2 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT8 pin configuration, PIN = Y4 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* CAMERA_DAT9 pin configuration, PIN = V6 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
}
|
|
|
|
/****************************************
|
|
* Routine: muxSetupMMCSD (ostboot)
|
|
* Description: set up MMC muxing
|
|
*****************************************/
|
|
void muxSetupMMCSD(void)
|
|
{
|
|
volatile unsigned char *MuxConfigReg;
|
|
|
|
/* SDMMC_CLKI pin configuration, PIN = H15 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_CLKO pin configuration, PIN = G19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_CMD pin configuration, PIN = H18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
/* External pull-ups are present. */
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
|
|
|
|
/* SDMMC_DAT0 pin configuration, PIN = F20 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
/* External pull-ups are present. */
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
|
|
|
|
/* SDMMC_DAT1 pin configuration, PIN = H14 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
/* External pull-ups are present. */
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
|
|
|
|
/* SDMMC_DAT2 pin configuration, PIN = E19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
/* External pull-ups are present. */
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
|
|
|
|
/* SDMMC_DAT3 pin configuration, PIN = D19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
/* External pull-ups are present. */
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
|
|
|
|
/* SDMMC_DDIR0 pin configuration, PIN = F19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_DDIR1 pin configuration, PIN = E20 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_DDIR2 pin configuration, PIN = F18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_DDIR3 pin configuration, PIN = E18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_CDIR pin configuration, PIN = G18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
|
|
/* MMC_CD for 2422IP=K1 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
|
|
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
|
|
|
|
/* MMC_WP pin configuration, PIN = B4 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
|
|
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
|
|
}
|
|
|
|
/******************************************
|
|
* Routine: muxSetupTouchScreen (ostboot)
|
|
* Description: Set up touch screen muxing
|
|
*******************************************/
|
|
void muxSetupTouchScreen(void)
|
|
{
|
|
volatile unsigned char *MuxConfigReg;
|
|
|
|
/* SPI1_CLK pin configuration, PIN = U18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_MOSI pin configuration, PIN = V20 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_MISO pin configuration, PIN = T18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_nCS0 pin configuration, PIN = U19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* PEN_IRQ pin configuration, PIN = P20 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
|
|
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
|
|
}
|
|
|
|
/****************************************
|
|
* Routine: muxSetupHDQ (ostboot)
|
|
* Description: setup 1wire mux
|
|
*****************************************/
|
|
void muxSetupHDQ(void)
|
|
{
|
|
volatile unsigned char *MuxConfigReg;
|
|
|
|
/* HDQ_SIO pin configuration, PIN = N18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
|
|
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
|
|
}
|
|
|
|
/***************************************************************
|
|
* Routine: muxSetupGPMC (ostboot)
|
|
* Description: Configures balls which cam up in protected mode
|
|
***************************************************************/
|
|
void muxSetupGPMC(void)
|
|
{
|
|
volatile uint8 *MuxConfigReg;
|
|
volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
|
|
|
|
/* gpmc_io_dir */
|
|
*MCR = 0x19000000;
|
|
|
|
/* NOR FLASH CS0 */
|
|
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
|
|
*MuxConfigReg = 0x00 ;
|
|
|
|
/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
|
|
*MuxConfigReg = 0x01 ;
|
|
|
|
/* MPDB(Multi Port Debug Port) CS1 */
|
|
/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
|
|
*MuxConfigReg = 0x00 ;
|
|
|
|
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
|
|
*MuxConfigReg = 0x00 ;
|
|
}
|
|
|
|
/****************************************************************
|
|
* Routine: muxSetupSDRC (ostboot)
|
|
* Description: Configures balls which come up in protected mode
|
|
****************************************************************/
|
|
void muxSetupSDRC(void)
|
|
{
|
|
volatile uint8 *MuxConfigReg;
|
|
|
|
/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
|
|
*MuxConfigReg = 0x00 ;
|
|
|
|
/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
|
|
*MuxConfigReg = 0x00 ;
|
|
|
|
/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
|
|
*MuxConfigReg = 0x00;
|
|
|
|
if (get_cpu_type() == CPU_2422) {
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
|
|
*MuxConfigReg = 0x1b;
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* Routine: update_mux()
|
|
* Description: Update balls which are different beween boards. All should be
|
|
* updated to match functionaly. However, I'm only updating ones
|
|
* which I'll be using for now. When power comes into play they
|
|
* all need updating.
|
|
*****************************************************************************/
|
|
void update_mux(u32 btype,u32 mtype)
|
|
{
|
|
u32 cpu, base = OMAP2420_CTRL_BASE;
|
|
cpu = get_cpu_type();
|
|
|
|
if (btype == BOARD_H4_MENELAUS) {
|
|
if (cpu == CPU_2420) {
|
|
/* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/
|
|
__raw_writeb(0x3, base+0x30);
|
|
/* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/
|
|
__raw_writeb(0x3, base+0xa3);
|
|
/* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
|
|
/* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
|
|
/* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
|
|
/* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
|
|
/* PIN = M1 (HSUSBOTG) */
|
|
/* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
|
|
__raw_writeb(0x3, base+0x9d);
|
|
/* PIN = U32, (WLAN_CLKREQ) */
|
|
/* PIN = Y11, WLAN */
|
|
/* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
|
|
__raw_writeb(0x3, base+0xe7);
|
|
/* PIN = AA8, mDOC */
|
|
/* PIN = AA10, BT */
|
|
/* PIN = AA13, WLAN */
|
|
/* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x10e);
|
|
/* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x110);
|
|
/* PIN = J15 HHUSB */
|
|
/* PIN = H19 HSUSB */
|
|
/* PIN = W13, P13, R13, W16 ... */
|
|
/* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0xde);
|
|
/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
|
|
__raw_writeb(0x0, base+0x12c);
|
|
/* PIN = AA17->sys_clkreq mode 0 -DO- */
|
|
__raw_writeb(0x0, base+0x136);
|
|
} else if (cpu == CPU_2422) {
|
|
/* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/
|
|
/* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
|
|
/* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
|
|
/* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
|
|
/* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
|
|
__raw_writeb(0x0, base+0x92);
|
|
/* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
|
|
/* PIN = M1 (HSUSBOTG) */
|
|
/* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
|
|
__raw_writeb(0x3, base+0x10c);
|
|
/* PIN = U32, (WLAN_CLKREQ) */
|
|
/* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
|
|
__raw_writeb(0x3, base+0x30);
|
|
/* PIN = AA8, mDOC */
|
|
/* PIN = AA10, BT */
|
|
/* PIN = AA12, WLAN */
|
|
/* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x10e);
|
|
/* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x110);
|
|
/* PIN = J15 HHUSB */
|
|
/* PIN = H19 HSUSB */
|
|
/* PIN = W13, P13, R13, W16 ... */
|
|
/* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0xde);
|
|
/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
|
|
__raw_writeb(0x0, base+0x12c);
|
|
/* PIN = AA17->sys_clkreq mode 0 -DO- */
|
|
__raw_writeb(0x0, base+0x136);
|
|
}
|
|
|
|
} else if (btype == BOARD_H4_SDP) {
|
|
if (cpu == CPU_2420) {
|
|
/* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/
|
|
/* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
|
|
/* Pin = Y11 VLNQ */
|
|
/* Pin = AA4 VLNQ */
|
|
/* Pin = AA6 VLNQ */
|
|
/* Pin = AA8 VLNQ */
|
|
/* Pin = AA10 VLNQ */
|
|
/* Pin = AA12 VLNQ */
|
|
/* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x10e);
|
|
/* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x110);
|
|
/* PIN = J15 MDOC_nDMAREQ */
|
|
/* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x114);
|
|
/* PIN = W13, V12, P13, R13, W19, W16 ... */
|
|
/* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
|
|
} else if (cpu == CPU_2422) {
|
|
/* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */
|
|
/* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/
|
|
/* Pin = Y11 VLNQ */
|
|
/* Pin = AA4 VLNQ */
|
|
/* Pin = AA6 VLNQ */
|
|
/* Pin = AA8 VLNQ */
|
|
/* Pin = AA10 VLNQ */
|
|
/* Pin = AA12 VLNQ */
|
|
/* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x10e);
|
|
/* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x110);
|
|
/* PIN = J15 MDOC_nDMAREQ */
|
|
/* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
|
|
__raw_writeb(0x3, base+0x114);
|
|
/* PIN = W13, V12, P13, R13, W19, W16 ... */
|
|
/* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
|
|
}
|
|
}
|
|
}
|
|
|
|
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
|
void nand_init(void)
|
|
{
|
|
extern flash_info_t flash_info[];
|
|
|
|
nand_probe(CFG_NAND_ADDR);
|
|
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
|
|
print_size(nand_dev_desc[0].totlen, "\n");
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}
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#ifdef CFG_JFFS2_MEM_NAND
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flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
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flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
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flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
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flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
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#endif
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}
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#endif
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