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https://github.com/AsahiLinux/u-boot
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819833af39
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
169 lines
3.6 KiB
C
169 lines
3.6 KiB
C
/*
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* linux/include/asm-arm/proc-armv/system.h
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*
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* Copyright (C) 1996 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_SYSTEM_H
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#define __ASM_PROC_SYSTEM_H
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#include <linux/config.h>
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/*
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* Save the current interrupt enable state & disable IRQs
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*/
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#define local_irq_save(x) \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_save\n" \
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" orr %1, %0, #128\n" \
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" msr cpsr_c, %1" \
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: "=r" (x), "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Enable IRQs
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*/
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#define local_irq_enable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_enable\n" \
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" bic %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Disable IRQs
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*/
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#define local_irq_disable() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_irq_disable\n" \
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" orr %0, %0, #128\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Enable FIQs
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*/
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#define __stf() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ stf\n" \
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" bic %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Disable FIQs
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*/
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#define __clf() \
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({ \
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unsigned long temp; \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ clf\n" \
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" orr %0, %0, #64\n" \
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" msr cpsr_c, %0" \
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: "=r" (temp) \
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: \
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: "memory"); \
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})
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/*
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* Save the current interrupt enable state.
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*/
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#define local_save_flags(x) \
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({ \
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__asm__ __volatile__( \
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"mrs %0, cpsr @ local_save_flags\n" \
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: "=r" (x) \
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: \
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: "memory"); \
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})
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/*
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* restore saved IRQ & FIQ state
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*/
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#define local_irq_restore(x) \
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__asm__ __volatile__( \
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"msr cpsr_c, %0 @ local_irq_restore\n" \
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: \
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: "r" (x) \
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: "memory")
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#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
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/*
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* On the StrongARM, "swp" is terminally broken since it bypasses the
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* cache totally. This means that the cache becomes inconsistent, and,
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* since we use normal loads/stores as well, this is really bad.
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* Typically, this causes oopsen in filp_close, but could have other,
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* more disasterous effects. There are two work-arounds:
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* 1. Disable interrupts and emulate the atomic swap
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* 2. Clean the cache, perform atomic swap, flush the cache
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*
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* We choose (1) since its the "easiest" to achieve here and is not
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* dependent on the processor type.
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*/
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#define swp_is_buggy
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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unsigned long ret;
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#ifdef swp_is_buggy
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unsigned long flags;
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#endif
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switch (size) {
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#ifdef swp_is_buggy
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case 1:
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local_irq_save(flags);
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ret = *(volatile unsigned char *)ptr;
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*(volatile unsigned char *)ptr = x;
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local_irq_restore(flags);
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break;
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case 4:
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local_irq_save(flags);
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ret = *(volatile unsigned long *)ptr;
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*(volatile unsigned long *)ptr = x;
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local_irq_restore(flags);
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break;
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#else
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case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory");
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break;
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case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory");
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break;
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#endif
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default: __bad_xchg(ptr, size), ret = 0;
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}
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return ret;
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}
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#endif
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