mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
ee73135365
Synced from Linux commit 3650b228f83a ("Linux 5.10-rc1")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
101 lines
2.3 KiB
Text
101 lines
2.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/dts-v1/;
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#include "meson-sm1.dtsi"
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#include "meson-khadas-vim3.dtsi"
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#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
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/ {
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compatible = "khadas,vim3l", "amlogic,sm1";
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model = "Khadas VIM3L";
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vddcpu: regulator-vddcpu {
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/*
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* Silergy SY8030DEC Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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vin-supply = <&vsys_3v3>;
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pwms = <&pwm_AO_cd 1 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU1_CLK>;
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clock-latency = <50000>;
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};
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&cpu2 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU2_CLK>;
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clock-latency = <50000>;
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};
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&cpu3 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU3_CLK>;
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clock-latency = <50000>;
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};
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&pwm_AO_cd {
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pinctrl-0 = <&pwm_ao_d_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin1";
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status = "okay";
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};
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/*
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* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
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* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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* an USB3.0 Type A connector and a M.2 Key M slot.
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* The PHY driving these differential lines is shared between
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* the USB3.0 controller and the PCIe Controller, thus only
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* a single controller can use it.
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* If the MCU is configured to mux the PCIe/USB3.0 differential lines
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* to the M.2 Key M slot, uncomment the following block to disable
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* USB3.0 from the USB Complex and enable the PCIe controller.
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* The End User is not expected to uncomment the following except for
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* testing purposes, but instead rely on the firmware/bootloader to
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* update these nodes accordingly if PCIe mode is selected by the MCU.
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*/
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/*
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&pcie {
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status = "okay";
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};
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&sd_emmc_a {
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sd-uhs-sdr50;
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};
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&usb {
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phys = <&usb2_phy0>, <&usb2_phy1>;
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phy-names = "usb2-phy0", "usb2-phy1";
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};
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*/
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