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https://github.com/AsahiLinux/u-boot
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ff6d1948dc
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type from bootstrap register must be ignored, and always be assumed as DDR1. This patch fixes the displayed DDR type of mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Stefan Roese <sr@denx.de>
113 lines
2.5 KiB
C
113 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt7628-clk.h>
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#include <linux/io.h>
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#include "mt7628.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void set_init_timer_freq(void)
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{
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void __iomem *sysc;
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u32 bs, val, timer_freq_post;
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sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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/* We can't use the clk driver as the DM has not been initialized yet */
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bs = readl(sysc + SYSCTL_SYSCFG0_REG);
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if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) {
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gd->arch.timer_freq = 25000000;
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timer_freq_post = 575000000;
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} else {
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gd->arch.timer_freq = 40000000;
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timer_freq_post = 580000000;
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}
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val = readl(sysc + SYSCTL_CLKCFG0_REG);
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if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)))
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gd->arch.timer_freq = timer_freq_post;
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}
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void mt7628_init(void)
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{
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set_init_timer_freq();
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mt7628_ddr_init();
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}
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int print_cpuinfo(void)
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{
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void __iomem *sysc;
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struct udevice *clkdev;
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u32 val, ver, eco, pkg, ddr, chipmode, ee;
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ulong cpu_clk, bus_clk, xtal_clk, timer_freq;
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struct clk clk;
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int ret;
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sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
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ver = (val & VER_M) >> VER_S;
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eco = (val & ECO_M) >> ECO_S;
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pkg = !!(val & PKG_ID);
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val = readl(sysc + SYSCTL_SYSCFG0_REG);
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ddr = val & DRAM_TYPE;
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chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
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val = readl(sysc + SYSCTL_EFUSE_CFG_REG);
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ee = val & EFUSE_MT7688;
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if (pkg == PKG_ID_KN)
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ddr = DRAM_DDR1;
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printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n",
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ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco);
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printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n",
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ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
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chipmode & 0x02 ? "XTAL" : "CPLL");
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ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk),
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&clkdev);
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if (ret)
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return ret;
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clk.dev = clkdev;
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clk.id = CLK_CPU;
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cpu_clk = clk_get_rate(&clk);
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clk.id = CLK_SYS;
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bus_clk = clk_get_rate(&clk);
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clk.id = CLK_XTAL;
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xtal_clk = clk_get_rate(&clk);
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clk.id = CLK_MIPS_CNT;
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timer_freq = clk_get_rate(&clk);
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/* Set final timer frequency */
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if (timer_freq)
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gd->arch.timer_freq = timer_freq;
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printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n",
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cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
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return 0;
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}
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ulong notrace get_tbclk(void)
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{
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return gd->arch.timer_freq;
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}
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