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https://github.com/AsahiLinux/u-boot
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f1218f0b4f
Add clk-main driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
387 lines
8.3 KiB
C
387 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Main clock support for AT91 architectures.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/clk-main.c from Linux.
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*/
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#include <asm/processor.h>
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_MAIN_RC "at91-main-rc-clk"
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#define UBOOT_DM_CLK_AT91_MAIN_OSC "at91-main-osc-clk"
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#define UBOOT_DM_CLK_AT91_RM9200_MAIN "at91-rm9200-main-clk"
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#define UBOOT_DM_CLK_AT91_SAM9X5_MAIN "at91-sam9x5-main-clk"
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#define MOR_KEY_MASK GENMASK(23, 16)
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#define USEC_PER_SEC 1000000UL
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#define SLOW_CLOCK_FREQ 32768
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#define clk_main_parent_select(s) (((s) & \
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(AT91_PMC_MOSCEN | \
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AT91_PMC_OSCBYPASS)) ? 1 : 0)
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struct clk_main_rc {
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void __iomem *reg;
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struct clk clk;
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};
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#define to_clk_main_rc(_clk) container_of(_clk, struct clk_main_rc, clk)
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struct clk_main_osc {
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void __iomem *reg;
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struct clk clk;
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};
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#define to_clk_main_osc(_clk) container_of(_clk, struct clk_main_osc, clk)
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struct clk_main {
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void __iomem *reg;
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const unsigned int *clk_mux_table;
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const char * const *parent_names;
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unsigned int num_parents;
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int type;
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struct clk clk;
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};
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#define to_clk_main(_clk) container_of(_clk, struct clk_main, clk)
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static int main_rc_enable(struct clk *clk)
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{
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struct clk_main_rc *main_rc = to_clk_main_rc(clk);
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void __iomem *reg = main_rc->reg;
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unsigned int val;
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pmc_read(reg, AT91_CKGR_MOR, &val);
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if (!(val & AT91_PMC_MOSCRCEN)) {
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pmc_update_bits(reg, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
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AT91_PMC_KEY | AT91_PMC_MOSCRCEN);
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}
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pmc_read(reg, AT91_PMC_SR, &val);
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while (!(val & AT91_PMC_MOSCRCS)) {
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pmc_read(reg, AT91_PMC_SR, &val);
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debug("waiting for main rc...\n");
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cpu_relax();
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}
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return 0;
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}
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static int main_rc_disable(struct clk *clk)
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{
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struct clk_main_rc *main_rc = to_clk_main_rc(clk);
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struct reg *reg = main_rc->reg;
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unsigned int val;
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pmc_read(reg, AT91_CKGR_MOR, &val);
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if (!(val & AT91_PMC_MOSCRCEN))
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return 0;
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pmc_update_bits(reg, AT91_CKGR_MOR, MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
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AT91_PMC_KEY);
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return 0;
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}
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static const struct clk_ops main_rc_clk_ops = {
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.enable = main_rc_enable,
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.disable = main_rc_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
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const char *parent_name)
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{
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struct clk_main_rc *main_rc;
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struct clk *clk;
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int ret;
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if (!reg || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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main_rc = kzalloc(sizeof(*main_rc), GFP_KERNEL);
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if (!main_rc)
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return ERR_PTR(-ENOMEM);
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main_rc->reg = reg;
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clk = &main_rc->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MAIN_RC, name,
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parent_name);
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if (ret) {
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kfree(main_rc);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_main_rc_clk) = {
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.name = UBOOT_DM_CLK_AT91_MAIN_RC,
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.id = UCLASS_CLK,
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.ops = &main_rc_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static int clk_main_osc_enable(struct clk *clk)
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{
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struct clk_main_osc *main = to_clk_main_osc(clk);
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void __iomem *reg = main->reg;
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unsigned int val;
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pmc_read(reg, AT91_CKGR_MOR, &val);
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val &= ~MOR_KEY_MASK;
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if (val & AT91_PMC_OSCBYPASS)
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return 0;
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if (!(val & AT91_PMC_MOSCEN)) {
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val |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
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pmc_write(reg, AT91_CKGR_MOR, val);
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}
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pmc_read(reg, AT91_PMC_SR, &val);
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while (!(val & AT91_PMC_MOSCS)) {
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pmc_read(reg, AT91_PMC_SR, &val);
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debug("waiting for main osc..\n");
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cpu_relax();
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}
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return 0;
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}
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static int clk_main_osc_disable(struct clk *clk)
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{
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struct clk_main_osc *main = to_clk_main_osc(clk);
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void __iomem *reg = main->reg;
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unsigned int val;
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pmc_read(reg, AT91_CKGR_MOR, &val);
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if (val & AT91_PMC_OSCBYPASS)
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return 0;
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if (!(val & AT91_PMC_MOSCEN))
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return 0;
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val &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
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pmc_write(reg, AT91_CKGR_MOR, val | AT91_PMC_KEY);
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return 0;
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}
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static const struct clk_ops main_osc_clk_ops = {
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.enable = clk_main_osc_enable,
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.disable = clk_main_osc_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *at91_clk_main_osc(void __iomem *reg, const char *name,
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const char *parent_name, bool bypass)
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{
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struct clk_main_osc *main;
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struct clk *clk;
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int ret;
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if (!reg || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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main = kzalloc(sizeof(*main), GFP_KERNEL);
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if (!main)
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return ERR_PTR(-ENOMEM);
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main->reg = reg;
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clk = &main->clk;
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if (bypass) {
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pmc_update_bits(reg, AT91_CKGR_MOR,
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MOR_KEY_MASK | AT91_PMC_OSCBYPASS,
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AT91_PMC_KEY | AT91_PMC_OSCBYPASS);
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}
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MAIN_OSC, name, parent_name);
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if (ret) {
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kfree(main);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_main_osc_clk) = {
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.name = UBOOT_DM_CLK_AT91_MAIN_OSC,
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.id = UCLASS_CLK,
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.ops = &main_osc_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static int clk_main_probe_frequency(void __iomem *reg)
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{
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unsigned int cycles = 16;
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unsigned int cycle = DIV_ROUND_UP(USEC_PER_SEC, SLOW_CLOCK_FREQ);
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unsigned int mcfr;
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while (cycles--) {
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pmc_read(reg, AT91_CKGR_MCFR, &mcfr);
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if (mcfr & AT91_PMC_MAINRDY)
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return 0;
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udelay(cycle);
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}
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return -ETIMEDOUT;
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}
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static int clk_rm9200_main_enable(struct clk *clk)
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{
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struct clk_main *main = to_clk_main(clk);
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return clk_main_probe_frequency(main->reg);
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}
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static const struct clk_ops rm9200_main_clk_ops = {
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.enable = clk_rm9200_main_enable,
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};
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struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name,
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const char *parent_name)
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{
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struct clk_main *main;
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struct clk *clk;
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int ret;
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if (!reg || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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main = kzalloc(sizeof(*main), GFP_KERNEL);
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if (!main)
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return ERR_PTR(-ENOMEM);
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main->reg = reg;
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clk = &main->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_RM9200_MAIN, name,
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parent_name);
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if (ret) {
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kfree(main);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_rm9200_main_clk) = {
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.name = UBOOT_DM_CLK_AT91_RM9200_MAIN,
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.id = UCLASS_CLK,
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.ops = &rm9200_main_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static inline bool clk_sam9x5_main_ready(void __iomem *reg)
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{
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unsigned int val;
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pmc_read(reg, AT91_PMC_SR, &val);
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return !!(val & AT91_PMC_MOSCSELS);
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}
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static int clk_sam9x5_main_enable(struct clk *clk)
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{
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struct clk_main *main = to_clk_main(clk);
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void __iomem *reg = main->reg;
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while (!clk_sam9x5_main_ready(reg)) {
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debug("waiting for main...");
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cpu_relax();
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}
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return clk_main_probe_frequency(reg);
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}
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static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_main *main = to_clk_main(clk);
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void __iomem *reg = main->reg;
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unsigned int tmp, index;
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index = at91_clk_mux_val_to_index(main->clk_mux_table,
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main->num_parents, AT91_CLK_ID_TO_DID(parent->id));
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if (index < 0)
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return index;
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pmc_read(reg, AT91_CKGR_MOR, &tmp);
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tmp &= ~MOR_KEY_MASK;
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tmp |= AT91_PMC_KEY;
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if (index && !(tmp & AT91_PMC_MOSCSEL))
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pmc_write(reg, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
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else if (!index && (tmp & AT91_PMC_MOSCSEL))
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pmc_write(reg, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
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while (!clk_sam9x5_main_ready(reg))
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cpu_relax();
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return 0;
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}
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static const struct clk_ops sam9x5_main_clk_ops = {
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.enable = clk_sam9x5_main_enable,
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.set_parent = clk_sam9x5_main_set_parent,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name,
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const char * const *parent_names,
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int num_parents, const u32 *clk_mux_table,
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int type)
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{
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struct clk *clk = ERR_PTR(-ENOMEM);
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struct clk_main *main = NULL;
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unsigned int val;
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int ret;
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if (!reg || !name || !parent_names || !num_parents || !clk_mux_table)
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return ERR_PTR(-EINVAL);
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main = kzalloc(sizeof(*main), GFP_KERNEL);
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if (!main)
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return ERR_PTR(-ENOMEM);
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main->reg = reg;
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main->parent_names = parent_names;
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main->num_parents = num_parents;
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main->clk_mux_table = clk_mux_table;
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main->type = type;
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clk = &main->clk;
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clk->flags = CLK_GET_RATE_NOCACHE;
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pmc_read(reg, AT91_CKGR_MOR, &val);
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X5_MAIN, name,
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main->parent_names[clk_main_parent_select(val)]);
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if (ret) {
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kfree(main);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_sam9x5_main_clk) = {
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.name = UBOOT_DM_CLK_AT91_SAM9X5_MAIN,
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.id = UCLASS_CLK,
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.ops = &sam9x5_main_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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