mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
098dbcb7ca
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # Paz00 Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
452 lines
11 KiB
C
452 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <panel.h>
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#include <part.h>
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#include <pwm.h>
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#include <video.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/display.h>
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#include <asm/arch-tegra/timer.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Information about the display controller */
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struct tegra_lcd_priv {
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int width; /* width in pixels */
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int height; /* height in pixels */
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enum video_log2_bpp log2_bpp; /* colour depth */
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struct display_timing timing;
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struct udevice *panel;
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struct dc_ctlr *dc; /* Display controller regmap */
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fdt_addr_t frame_buffer; /* Address of frame buffer */
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unsigned pixel_clock; /* Pixel clock in Hz */
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int dc_clk[2]; /* Contains clk and its parent */
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};
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1920,
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LCD_MAX_HEIGHT = 1200,
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LCD_MAX_LOG2_BPP = VIDEO_BPP16,
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};
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static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
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{
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unsigned h_dda, v_dda;
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unsigned long val;
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val = readl(&dc->cmd.disp_win_header);
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val |= WINDOW_A_SELECT;
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writel(val, &dc->cmd.disp_win_header);
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writel(win->fmt, &dc->win.color_depth);
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clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
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BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
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val = win->out_x << H_POSITION_SHIFT;
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val |= win->out_y << V_POSITION_SHIFT;
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writel(val, &dc->win.pos);
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val = win->out_w << H_SIZE_SHIFT;
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val |= win->out_h << V_SIZE_SHIFT;
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writel(val, &dc->win.size);
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val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
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val |= win->h << V_PRESCALED_SIZE_SHIFT;
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writel(val, &dc->win.prescaled_size);
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writel(0, &dc->win.h_initial_dda);
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writel(0, &dc->win.v_initial_dda);
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h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
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v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
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val = h_dda << H_DDA_INC_SHIFT;
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val |= v_dda << V_DDA_INC_SHIFT;
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writel(val, &dc->win.dda_increment);
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writel(win->stride, &dc->win.line_stride);
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writel(0, &dc->win.buf_stride);
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val = WIN_ENABLE;
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if (win->bpp < 24)
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val |= COLOR_EXPAND;
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writel(val, &dc->win.win_opt);
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writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
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writel(win->x, &dc->winbuf.addr_h_offset);
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writel(win->y, &dc->winbuf.addr_v_offset);
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writel(0xff00, &dc->win.blend_nokey);
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writel(0xff00, &dc->win.blend_1win);
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
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val |= GENERAL_UPDATE | WIN_A_UPDATE;
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writel(val, &dc->cmd.state_ctrl);
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}
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static int update_display_mode(struct dc_disp_reg *disp,
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struct tegra_lcd_priv *priv)
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{
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struct display_timing *dt = &priv->timing;
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unsigned long val;
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unsigned long rate;
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unsigned long div;
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writel(0x0, &disp->disp_timing_opt);
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writel(1 | 1 << 16, &disp->ref_to_sync);
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writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
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writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
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&disp->back_porch);
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writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
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&disp->front_porch);
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writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
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val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
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val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
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writel(val, &disp->data_enable_opt);
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val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
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val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
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val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
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writel(val, &disp->disp_interface_ctrl);
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/*
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* The pixel clock divider is in 7.1 format (where the bottom bit
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* represents 0.5). Here we calculate the divider needed to get from
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* the display clock (typically 600MHz) to the pixel clock. We round
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* up or down as requried.
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*/
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rate = clock_get_periph_rate(priv->dc_clk[0], priv->dc_clk[1]);
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div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
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debug("Display clock %lu, divider %lu\n", rate, div);
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writel(0x00010001, &disp->shift_clk_opt);
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val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
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val |= div << SHIFT_CLK_DIVIDER_SHIFT;
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writel(val, &disp->disp_clk_ctrl);
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return 0;
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}
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/* Start up the display and turn on power to PWMs */
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static void basic_init(struct dc_cmd_reg *cmd)
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{
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u32 val;
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writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
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writel(0x0000011a, &cmd->cont_syncpt_vsync);
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writel(0x00000000, &cmd->int_type);
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writel(0x00000000, &cmd->int_polarity);
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writel(0x00000000, &cmd->int_mask);
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writel(0x00000000, &cmd->int_enb);
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val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
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val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
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val |= PM1_ENABLE;
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writel(val, &cmd->disp_pow_ctrl);
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val = readl(&cmd->disp_cmd);
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val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
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writel(val, &cmd->disp_cmd);
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}
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static void basic_init_timer(struct dc_disp_reg *disp)
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{
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writel(0x00000020, &disp->mem_high_pri);
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writel(0x00000001, &disp->mem_high_pri_timer);
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}
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static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x01000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_data_tab[PIN_REG_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00210222,
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0x00002200,
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0x00020000,
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};
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static void rgb_enable(struct dc_com_reg *com)
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{
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int i;
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for (i = 0; i < PIN_REG_COUNT; i++) {
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writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
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writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
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writel(rgb_data_tab[i], &com->pin_output_data[i]);
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}
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for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
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writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
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}
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static int setup_window(struct disp_ctl_win *win,
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struct tegra_lcd_priv *priv)
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{
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win->x = 0;
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win->y = 0;
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win->w = priv->width;
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win->h = priv->height;
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win->out_x = 0;
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win->out_y = 0;
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win->out_w = priv->width;
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win->out_h = priv->height;
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win->phys_addr = priv->frame_buffer;
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win->stride = priv->width * (1 << priv->log2_bpp) / 8;
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debug("%s: depth = %d\n", __func__, priv->log2_bpp);
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switch (priv->log2_bpp) {
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case VIDEO_BPP32:
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win->fmt = COLOR_DEPTH_R8G8B8A8;
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win->bpp = 32;
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break;
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case VIDEO_BPP16:
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win->fmt = COLOR_DEPTH_B5G6R5;
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win->bpp = 16;
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break;
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default:
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debug("Unsupported LCD bit depth");
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return -1;
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}
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return 0;
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}
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/**
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* Register a new display based on device tree configuration.
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*
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* The frame buffer can be positioned by U-Boot or overridden by the fdt.
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* You should pass in the U-Boot address here, and check the contents of
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* struct tegra_lcd_priv to see what was actually chosen.
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*
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* @param blob Device tree blob
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* @param priv Driver's private data
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* @param default_lcd_base Default address of LCD frame buffer
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* Return: 0 if ok, -1 on error (unsupported bits per pixel)
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*/
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static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
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void *default_lcd_base)
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{
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struct disp_ctl_win window;
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unsigned long rate = clock_get_rate(priv->dc_clk[1]);
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priv->frame_buffer = (u32)default_lcd_base;
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/*
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* We halve the rate if DISP1 paret is PLLD, since actual parent
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* is plld_out0 which is PLLD divided by 2.
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*/
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if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
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rate /= 2;
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/*
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* HOST1X is init by default at 150MHz with PLLC as parent
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*/
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clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL,
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150 * 1000000);
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clock_start_periph_pll(priv->dc_clk[0], priv->dc_clk[1],
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rate);
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basic_init(&priv->dc->cmd);
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basic_init_timer(&priv->dc->disp);
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rgb_enable(&priv->dc->com);
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if (priv->pixel_clock)
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update_display_mode(&priv->dc->disp, priv);
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if (setup_window(&window, priv))
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return -1;
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update_window(priv->dc, &window);
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return 0;
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}
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static int tegra_lcd_probe(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct tegra_lcd_priv *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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int ret;
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/* Initialize the Tegra display controller */
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#ifdef CONFIG_TEGRA20
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funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
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#endif
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if (tegra_display_probe(blob, priv, (void *)plat->base)) {
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printf("%s: Failed to probe display driver\n", __func__);
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return -1;
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}
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#ifdef CONFIG_TEGRA20
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pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
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pinmux_tristate_disable(PMUX_PINGRP_GPU);
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#endif
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ret = panel_enable_backlight(priv->panel);
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if (ret) {
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debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
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return ret;
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}
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mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
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DCACHE_WRITETHROUGH);
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/* Enable flushing after LCD writes if requested */
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video_set_flush_dcache(dev, true);
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uc_priv->xsize = priv->width;
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uc_priv->ysize = priv->height;
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uc_priv->bpix = priv->log2_bpp;
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debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
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plat->size);
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return 0;
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}
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static int tegra_lcd_of_to_plat(struct udevice *dev)
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{
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struct tegra_lcd_priv *priv = dev_get_priv(dev);
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const void *blob = gd->fdt_blob;
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struct display_timing *timing;
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int node = dev_of_offset(dev);
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int panel_node;
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int rgb;
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int ret;
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priv->dc = (struct dc_ctlr *)dev_read_addr_ptr(dev);
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if (!priv->dc) {
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debug("%s: No display controller address\n", __func__);
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return -EINVAL;
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}
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ret = clock_decode_pair(dev, priv->dc_clk);
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if (ret < 0) {
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debug("%s: Cannot decode clocks for '%s' (ret = %d)\n",
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__func__, dev->name, ret);
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return -EINVAL;
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}
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rgb = fdt_subnode_offset(blob, node, "rgb");
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if (rgb < 0) {
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debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
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__func__, dev->name, rgb);
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return -EINVAL;
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}
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/*
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* Sadly the panel phandle is in an rgb subnode so we cannot use
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* uclass_get_device_by_phandle().
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*/
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panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
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if (panel_node < 0) {
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debug("%s: Cannot find panel information\n", __func__);
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return -EINVAL;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
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&priv->panel);
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if (ret) {
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debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
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dev->name, ret);
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return ret;
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}
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ret = panel_get_display_timing(priv->panel, &priv->timing);
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if (ret) {
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ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
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if (ret) {
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debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
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__func__, dev->name, ret);
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return -EINVAL;
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}
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}
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timing = &priv->timing;
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priv->width = timing->hactive.typ;
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priv->height = timing->vactive.typ;
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priv->pixel_clock = timing->pixelclock.typ;
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priv->log2_bpp = VIDEO_BPP16;
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return 0;
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}
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static int tegra_lcd_bind(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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int rgb;
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rgb = fdt_subnode_offset(blob, node, "rgb");
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if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
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return -ENODEV;
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plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
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(1 << LCD_MAX_LOG2_BPP) / 8;
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return 0;
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}
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static const struct video_ops tegra_lcd_ops = {
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};
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static const struct udevice_id tegra_lcd_ids[] = {
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{ .compatible = "nvidia,tegra20-dc" },
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{ .compatible = "nvidia,tegra30-dc" },
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{ }
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};
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U_BOOT_DRIVER(tegra_lcd) = {
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.name = "tegra_lcd",
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.id = UCLASS_VIDEO,
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.of_match = tegra_lcd_ids,
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.ops = &tegra_lcd_ops,
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.bind = tegra_lcd_bind,
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.probe = tegra_lcd_probe,
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.of_to_plat = tegra_lcd_of_to_plat,
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.priv_auto = sizeof(struct tegra_lcd_priv),
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};
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