mirror of
https://github.com/AsahiLinux/u-boot
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ff3e8b8c6c
Heavily based on Linux kernel Samsung clock framework, with some changes to accommodate the differences in U-Boot CCF implementation. It's also quite minimal as compared to the Linux version. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023 Linaro Ltd.
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* Sam Protsenko <semen.protsenko@linaro.org>
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*
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* This file includes utility functions to register clocks to common
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* clock framework for Samsung platforms.
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*/
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#include <dm.h>
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#include "clk.h"
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void samsung_clk_register_mux(void __iomem *base,
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const struct samsung_mux_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_mux_clock *m;
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m = &clk_list[cnt];
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clk = clk_register_mux(NULL, m->name, m->parent_names,
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m->num_parents, m->flags, base + m->offset, m->shift,
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m->width, m->mux_flags);
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clk_dm(m->id, clk);
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}
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}
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void samsung_clk_register_div(void __iomem *base,
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const struct samsung_div_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_div_clock *d;
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d = &clk_list[cnt];
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clk = clk_register_divider(NULL, d->name, d->parent_name,
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d->flags, base + d->offset, d->shift,
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d->width, d->div_flags);
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clk_dm(d->id, clk);
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}
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}
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void samsung_clk_register_gate(void __iomem *base,
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const struct samsung_gate_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_gate_clock *g;
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g = &clk_list[cnt];
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clk = clk_register_gate(NULL, g->name, g->parent_name,
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g->flags, base + g->offset, g->bit_idx,
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g->gate_flags, NULL);
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clk_dm(g->id, clk);
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}
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}
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typedef void (*samsung_clk_register_fn)(void __iomem *base,
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const void *clk_list,
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unsigned int nr_clk);
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static const samsung_clk_register_fn samsung_clk_register_fns[] = {
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[S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux,
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[S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div,
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[S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate,
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[S_CLK_PLL] = (samsung_clk_register_fn)samsung_clk_register_pll,
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};
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/**
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* samsung_cmu_register_clocks() - Register provided clock groups
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* @base: Base address of CMU registers
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* @clk_groups: list of clock groups
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* @nr_groups: count of clock groups in @clk_groups
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*
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* Having the array of clock groups @clk_groups makes it possible to keep a
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* correct clocks registration order.
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*/
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void samsung_cmu_register_clocks(void __iomem *base,
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const struct samsung_clk_group *clk_groups,
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unsigned int nr_groups)
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{
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unsigned int i;
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for (i = 0; i < nr_groups; i++) {
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const struct samsung_clk_group *g = &clk_groups[i];
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samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk);
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}
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}
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/**
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* samsung_cmu_register_one - Register all CMU clocks
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* @dev: CMU device
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* @clk_groups: list of CMU clock groups
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* @nr_groups: count of CMU clock groups in @clk_groups
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*
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* Return: 0 on success or negative value on error.
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*/
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int samsung_cmu_register_one(struct udevice *dev,
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const struct samsung_clk_group *clk_groups,
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unsigned int nr_groups)
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{
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void __iomem *base;
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base = dev_read_addr_ptr(dev);
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if (!base)
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return -EINVAL;
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samsung_cmu_register_clocks(base, clk_groups, nr_groups);
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return 0;
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}
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