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096d471a76
add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
102 lines
2.9 KiB
ArmAsm
102 lines
2.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015, Linaro Limited
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* Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* Authors:
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* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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*/
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#include <linux/linkage.h>
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#include <linux/arm-smccc.h>
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#include <generated/asm-offsets.h>
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#ifdef CONFIG_EFI_LOADER
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.section .text.efi_runtime
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#endif
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.macro SMCCC instr
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.cfi_startproc
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\instr #0
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ldr x4, [sp]
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stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
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stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
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ldr x4, [sp, #8]
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cbz x4, 1f /* no quirk structure */
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ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
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cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
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b.ne 1f
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str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
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1: ret
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.cfi_endproc
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.endm
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/*
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* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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ENTRY(__arm_smccc_smc)
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SMCCC smc
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ENDPROC(__arm_smccc_smc)
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/*
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* void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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ENTRY(__arm_smccc_hvc)
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SMCCC hvc
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ENDPROC(__arm_smccc_hvc)
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#ifdef CONFIG_ARM64
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.macro SMCCC_1_2 instr
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/* Save `res` and free a GPR that won't be clobbered */
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stp x1, x19, [sp, #-16]!
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/* Ensure `args` won't be clobbered while loading regs in next step */
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mov x19, x0
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/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
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ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
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ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
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ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
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ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
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ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
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ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
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ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
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ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
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ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
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\instr #0
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/* Load the `res` from the stack */
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ldr x19, [sp]
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/* Store the registers x0 - x17 into the result structure */
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stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
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stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
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stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
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stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
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stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
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stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
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stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
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stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
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stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
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/* Restore original x19 */
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ldp xzr, x19, [sp], #16
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ret
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.endm
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/*
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* void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
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* struct arm_smccc_1_2_regs *res);
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*/
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ENTRY(arm_smccc_1_2_smc)
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SMCCC_1_2 smc
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ENDPROC(arm_smccc_1_2_smc)
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#endif
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