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3cf97f4543
This patch adds support for generic GPIO driver framework for Marvell SoC Armada100. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
48 lines
1.5 KiB
C
48 lines
1.5 KiB
C
/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef _ASM_ARCH_GPIO_H
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#define _ASM_ARCH_GPIO_H
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#include <asm/types.h>
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#include <asm/arch/armada100.h>
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#define GPIO_HIGH 1
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#define GPIO_LOW 0
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#define GPIO_TO_REG(gp) (gp >> 5)
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#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
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#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
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static inline void *get_gpio_base(int bank)
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{
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const unsigned int offset[4] = {0, 4, 8, 0x100};
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/* gpio register bank offset - refer Appendix A.36 */
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return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
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}
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#endif /* _ASM_ARCH_GPIO_H */
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