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https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
189 lines
6.1 KiB
C
189 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*
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* Configuration settings for the RONETIX PM9263 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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/* ARM asynchronous clock */
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#define MASTER_PLL_DIV 6
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#define MASTER_PLL_MUL 65
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#define MAIN_PLL_DIV 2 /* 2 or 4 */
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#define CFG_SYS_AT91_MAIN_CLOCK 18432000
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#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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/* clocks */
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#define CFG_SYS_MOR_VAL \
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(AT91_PMC_MOR_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CFG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_PLLXR_OUT(3) | \
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
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(2 << 28) | /* PLL Clock Frequency Range */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#if (MAIN_PLL_DIV == 2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CFG_SYS_MCKR1_VAL \
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(AT91_PMC_MCKR_CSS_SLOW | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CFG_SYS_MCKR2_VAL \
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(AT91_PMC_MCKR_CSS_PLLA | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_2)
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#else
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CFG_SYS_MCKR1_VAL \
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(AT91_PMC_MCKR_CSS_SLOW | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_4)
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/* PCK/4 = MCK Master Clock from PLLA */
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#define CFG_SYS_MCKR2_VAL \
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(AT91_PMC_MCKR_CSS_PLLA | \
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AT91_PMC_MCKR_PRES_1 | \
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AT91_PMC_MCKR_MDIV_4)
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#endif
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/* define PDC[31:16] as DATA[31:16] */
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#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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#define CFG_SYS_MATRIX_EBI0CSA_VAL \
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(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
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AT91_MATRIX_CSA_EBI_CS1A)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CFG_SYS_SDRC_MR_VAL1 0
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/* SDRAMC_TR - Refresh Timer register */
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#define CFG_SYS_SDRC_TR_VAL1 0x3AA
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/* SDRAMC_CR - Configuration register*/
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#define CFG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* tWR - Write Recovery Delay */ \
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(7 << 12) | /* tRC - Row Cycle Delay */ \
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(2 << 16) | /* tRP - Row Precharge Delay */ \
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(2 << 20) | /* tRCD - Row to Column Delay */ \
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(5 << 24) | /* tRAS - Active to Precharge Delay */ \
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(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
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/* Memory Device Register -> SDRAM */
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#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CFG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
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AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
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#define CFG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
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AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
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#define CFG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
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#define CFG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
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AT91_SMC_MODE_DBW_16 | \
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AT91_SMC_MODE_TDF | \
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AT91_SMC_MODE_TDF_CYCLE(6))
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/* user reset enable */
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#define CFG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_CR_PROCRST | \
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AT91_RSTC_MR_ERSTL(1) | \
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AT91_RSTC_MR_ERSTL(2))
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/* Disable Watchdog */
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#define CFG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
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AT91_WDT_MR_WDV(0xfff) | \
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AT91_WDT_MR_WDDIS | \
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AT91_WDT_MR_WDD(0xfff))
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/* SDRAM */
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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/* NOR flash, if populated */
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#define PHYS_FLASH_1 0x10000000
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#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CFG_SYS_NAND_BASE 0x40000000
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/* our ALE is AD21 */
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#define CFG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CFG_SYS_NAND_MASK_CLE (1 << 22)
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#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
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#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
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#endif
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/* PSRAM */
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#define PHYS_PSRAM 0x70000000
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#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
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/* Slave EBI1, PSRAM connected */
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#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
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AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
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AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
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AT91_MATRIX_SCFG_SLOT_CYCLE(255))
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/* USB */
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#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"partition=nand0,0\0" \
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"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"fbcon=rotate:3 " \
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"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
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":$(hostname):eth0:off\0" \
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"ramboot=tftpboot 0x22000000 vmImage;" \
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"run ramargs;run addip;bootm 22000000\0" \
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"nfsboot=tftpboot 0x22000000 vmImage;" \
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"run nfsargs;run addip;bootm 22000000\0" \
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"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
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""
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#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
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#endif
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