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https://github.com/AsahiLinux/u-boot
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97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __LPDDR4_DEFINE_H_
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#define __LPDDR4_DEFINE_H_
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#define LPDDR4_DVFS_DBI
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#define DDR_ONE_RANK
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/* #define LPDDR4_DBI_ON */
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#define DFI_BUG_WR
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#define M845S_4GBx2
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#define PRETRAIN
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/* DRAM MR setting */
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#ifdef LPDDR4_DBI_ON
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#define LPDDR4_MR3 0xf1
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#define LPDDR4_PHY_DMIPinPresent 0x1
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#else
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#define LPDDR4_MR3 0x31
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#define LPDDR4_PHY_DMIPinPresent 0x0
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#endif
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#ifdef DDR_ONE_RANK
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#define LPDDR4_CS 0x1
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#else
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#define LPDDR4_CS 0x3
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#endif
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/* PHY training feature */
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#define LPDDR4_HDT_CTL_2D 0xC8
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#define LPDDR4_HDT_CTL_3200_1D 0xC8
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#define LPDDR4_HDT_CTL_400_1D 0xC8
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#define LPDDR4_HDT_CTL_100_1D 0xC8
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/* 400/100 training seq */
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#define LPDDR4_TRAIN_SEQ_P2 0x121f
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#define LPDDR4_TRAIN_SEQ_P1 0x121f
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#define LPDDR4_TRAIN_SEQ_P0 0x121f
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#define LPDDR4_TRAIN_SEQ_100 0x121f
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#define LPDDR4_TRAIN_SEQ_400 0x121f
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/* 2D share & weight */
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#define LPDDR4_2D_WEIGHT 0x1f7f
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#define LPDDR4_2D_SHARE 1
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#define LPDDR4_CATRAIN_3200_1d 0
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#define LPDDR4_CATRAIN_400 0
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#define LPDDR4_CATRAIN_100 0
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#define LPDDR4_CATRAIN_3200_2d 0
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/* MRS parameter */
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/* for LPDDR4 Rtt */
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#define LPDDR4_RTT40 6
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#define LPDDR4_RTT48 5
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#define LPDDR4_RTT60 4
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#define LPDDR4_RTT80 3
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#define LPDDR4_RTT120 2
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#define LPDDR4_RTT240 1
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#define LPDDR4_RTT_DIS 0
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/* for LPDDR4 Ron */
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#define LPDDR4_RON34 7
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#define LPDDR4_RON40 6
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#define LPDDR4_RON48 5
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#define LPDDR4_RON60 4
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#define LPDDR4_RON80 3
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#define LPDDR4_PHY_ADDR_RON60 0x1
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#define LPDDR4_PHY_ADDR_RON40 0x3
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#define LPDDR4_PHY_ADDR_RON30 0x7
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#define LPDDR4_PHY_ADDR_RON24 0xf
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#define LPDDR4_PHY_ADDR_RON20 0x1f
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/* for read channel */
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#define LPDDR4_RON LPDDR4_RON40
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#define LPDDR4_PHY_RTT 30
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#define LPDDR4_PHY_VREF_VALUE 17
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/* for write channel */
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#define LPDDR4_PHY_RON 30
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#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
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#define LPDDR4_RTT_DQ LPDDR4_RTT40
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#define LPDDR4_RTT_CA LPDDR4_RTT40
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#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40
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#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40
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#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd))
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#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd))
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#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd))
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#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \
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(LPDDR4_RTT40))
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#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \
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(LPDDR4_RTT40))
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#define LPDDR4_MR3_PU_CAL 1
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#endif /* __LPDDR4_DEFINE_H__ */
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