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On mpc832x, SPI can be either handled by CPU or QE. In order to work in CPU mode, bit 17 of SPMODE has to be set to 1, that bit is called OP. Also, data is located at a different place than the one expected by the driver today. In 8 bits mode with REV set, data to be transmitted is located in the most significant byte while received data is located in second byte. So perform the necessary shifts. In order to differentiate with other CPUs, a new compatible is added for mpc832x: fsl,mpc832x-spi Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
32 lines
742 B
C
32 lines
742 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale non-CPM SPI Controller
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*
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* Copyright 2008 Qstreams Networks, Inc.
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*/
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#ifndef _ASM_MPC8XXX_SPI_H_
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#define _ASM_MPC8XXX_SPI_H_
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#include <asm/types.h>
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#if defined(CONFIG_ARCH_MPC8308) || \
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defined(CONFIG_ARCH_MPC8313) || \
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defined(CONFIG_ARCH_MPC832X) || \
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defined(CONFIG_ARCH_MPC834X) || \
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defined(CONFIG_ARCH_MPC837X)
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typedef struct spi8xxx {
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u8 res0[0x20]; /* 0x0-0x01f reserved */
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u32 mode; /* mode register */
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u32 event; /* event register */
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u32 mask; /* mask register */
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u32 com; /* command register */
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u32 tx; /* transmit register */
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u32 rx; /* receive register */
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u8 res1[0xFC8]; /* fill up to 0x1000 */
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} spi8xxx_t;
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#endif
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#endif /* _ASM_MPC8XXX_SPI_H_ */
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