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Import cvmx-sata-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
311 lines
7.3 KiB
C
311 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_SATA_DEFS_H__
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#define __CVMX_SATA_DEFS_H__
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#define CVMX_SATA_UCTL_CTL (0x000118006C000000ull)
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#define CVMX_SATA_UCTL_SHIM_CFG (0x000118006C0000E8ull)
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#define CVMX_SATA_UCTL_BIST_STATUS (0x000118006C000008ull)
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#define CVMX_SATA_UAHC_GBL_PI (0x00016C000000000Cull)
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#define CVMX_SATA_UAHC_GBL_TIMER1MS (0x00016C00000000E0ull)
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#define CVMX_SATA_UAHC_GBL_CAP (0x00016C0000000000ull)
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#define CVMX_SATA_UAHC_PX_CMD(offset) (0x00016C0000000118ull + ((offset) & 1) * 128)
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#define CVMX_SATA_UAHC_PX_SCTL(offset) (0x00016C000000012Cull + ((offset) & 1) * 128)
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#define CVMX_SATA_UAHC_PX_SERR(offset) (0x00016C0000000130ull + ((offset) & 1) * 128)
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#define CVMX_SATA_UAHC_PX_IS(offset) (0x00016C0000000110ull + ((offset) & 1) * 128)
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#define CVMX_SATA_UAHC_PX_SSTS(offset) (0x00016C0000000128ull + ((offset) & 1) * 128)
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#define CVMX_SATA_UAHC_PX_TFD(offset) (0x00016C0000000120ull + ((offset) & 1) * 128)
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/**
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* cvmx_sata_uctl_ctl
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*
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* This register controls clocks, resets, power, and BIST for the SATA.
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*
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* Accessible always.
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*
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* Reset by IOI reset.
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*/
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union cvmx_sata_uctl_ctl {
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u64 u64;
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struct cvmx_sata_uctl_ctl_s {
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u64 clear_bist : 1;
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u64 start_bist : 1;
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u64 reserved_31_61 : 31;
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u64 a_clk_en : 1;
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u64 a_clk_byp_sel : 1;
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u64 a_clkdiv_rst : 1;
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u64 reserved_27_27 : 1;
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u64 a_clkdiv_sel : 3;
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u64 reserved_5_23 : 19;
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u64 csclk_en : 1;
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u64 reserved_2_3 : 2;
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u64 sata_uahc_rst : 1;
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u64 sata_uctl_rst : 1;
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} s;
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struct cvmx_sata_uctl_ctl_s cn70xx;
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struct cvmx_sata_uctl_ctl_s cn70xxp1;
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struct cvmx_sata_uctl_ctl_s cn73xx;
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};
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typedef union cvmx_sata_uctl_ctl cvmx_sata_uctl_ctl_t;
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/**
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* cvmx_sata_uctl_bist_status
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*
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* Results from BIST runs of SATA's memories.
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* Wait for NDONE==0, then look at defect indication.
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*
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* Accessible always.
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*
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* Reset by IOI reset.
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*/
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union cvmx_sata_uctl_bist_status {
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u64 u64;
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struct cvmx_sata_uctl_bist_status_s {
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u64 reserved_42_63 : 22;
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u64 uctl_xm_r_bist_ndone : 1;
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u64 uctl_xm_w_bist_ndone : 1;
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u64 reserved_36_39 : 4;
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u64 uahc_p0_rxram_bist_ndone : 1;
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u64 uahc_p1_rxram_bist_ndone : 1;
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u64 uahc_p0_txram_bist_ndone : 1;
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u64 uahc_p1_txram_bist_ndone : 1;
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u64 reserved_10_31 : 22;
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u64 uctl_xm_r_bist_status : 1;
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u64 uctl_xm_w_bist_status : 1;
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u64 reserved_4_7 : 4;
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u64 uahc_p0_rxram_bist_status : 1;
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u64 uahc_p1_rxram_bist_status : 1;
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u64 uahc_p0_txram_bist_status : 1;
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u64 uahc_p1_txram_bist_status : 1;
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} s;
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struct cvmx_sata_uctl_bist_status_s cn70xx;
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struct cvmx_sata_uctl_bist_status_s cn70xxp1;
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struct cvmx_sata_uctl_bist_status_s cn73xx;
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};
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typedef union cvmx_sata_uctl_bist_status cvmx_sata_uctl_bist_status_t;
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/**
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* cvmx_sata_uctl_shim_cfg
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*
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* This register allows configuration of various shim (UCTL) features.
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*
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* Fields XS_NCB_OOB_* are captured when there are no outstanding OOB errors indicated in INTSTAT
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* and a new OOB error arrives.
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*
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* Fields XS_BAD_DMA_* are captured when there are no outstanding DMA errors indicated in INTSTAT
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* and a new DMA error arrives.
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*
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* Accessible only when SATA_UCTL_CTL[A_CLK_EN].
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*
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* Reset by IOI reset or SATA_UCTL_CTL[SATA_UCTL_RST].
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*/
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union cvmx_sata_uctl_shim_cfg {
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u64 u64;
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struct cvmx_sata_uctl_shim_cfg_s {
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u64 xs_ncb_oob_wrn : 1;
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u64 reserved_60_62 : 3;
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u64 xs_ncb_oob_osrc : 12;
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u64 xm_bad_dma_wrn : 1;
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u64 reserved_44_46 : 3;
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u64 xm_bad_dma_type : 4;
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u64 reserved_14_39 : 26;
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u64 dma_read_cmd : 2;
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u64 reserved_11_11 : 1;
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u64 dma_write_cmd : 1;
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u64 dma_endian_mode : 2;
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u64 reserved_2_7 : 6;
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u64 csr_endian_mode : 2;
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} s;
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struct cvmx_sata_uctl_shim_cfg_cn70xx {
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u64 xs_ncb_oob_wrn : 1;
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u64 reserved_57_62 : 6;
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u64 xs_ncb_oob_osrc : 9;
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u64 xm_bad_dma_wrn : 1;
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u64 reserved_44_46 : 3;
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u64 xm_bad_dma_type : 4;
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u64 reserved_13_39 : 27;
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u64 dma_read_cmd : 1;
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u64 reserved_10_11 : 2;
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u64 dma_endian_mode : 2;
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u64 reserved_2_7 : 6;
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u64 csr_endian_mode : 2;
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} cn70xx;
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struct cvmx_sata_uctl_shim_cfg_cn70xx cn70xxp1;
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struct cvmx_sata_uctl_shim_cfg_s cn73xx;
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};
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typedef union cvmx_sata_uctl_shim_cfg cvmx_sata_uctl_shim_cfg_t;
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/**
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* cvmx_sata_uahc_gbl_cap
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*
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* See AHCI specification v1.3 section 3.1
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*
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*/
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union cvmx_sata_uahc_gbl_cap {
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u32 u32;
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struct cvmx_sata_uahc_gbl_cap_s {
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u32 s64a : 1;
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u32 sncq : 1;
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u32 ssntf : 1;
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u32 smps : 1;
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u32 sss : 1;
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u32 salp : 1;
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u32 sal : 1;
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u32 sclo : 1;
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u32 iss : 4;
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u32 snzo : 1;
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u32 sam : 1;
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u32 spm : 1;
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u32 fbss : 1;
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u32 pmd : 1;
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u32 ssc : 1;
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u32 psc : 1;
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u32 ncs : 5;
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u32 cccs : 1;
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u32 ems : 1;
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u32 sxs : 1;
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u32 np : 5;
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} s;
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struct cvmx_sata_uahc_gbl_cap_s cn70xx;
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struct cvmx_sata_uahc_gbl_cap_s cn70xxp1;
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struct cvmx_sata_uahc_gbl_cap_s cn73xx;
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};
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typedef union cvmx_sata_uahc_gbl_cap cvmx_sata_uahc_gbl_cap_t;
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/**
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* cvmx_sata_uahc_p#_sctl
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*/
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union cvmx_sata_uahc_px_sctl {
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u32 u32;
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struct cvmx_sata_uahc_px_sctl_s {
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u32 reserved_10_31 : 22;
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u32 ipm : 2;
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u32 reserved_6_7 : 2;
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u32 spd : 2;
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u32 reserved_3_3 : 1;
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u32 det : 3;
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} s;
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struct cvmx_sata_uahc_px_sctl_s cn70xx;
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struct cvmx_sata_uahc_px_sctl_s cn70xxp1;
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struct cvmx_sata_uahc_px_sctl_s cn73xx;
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};
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typedef union cvmx_sata_uahc_px_sctl cvmx_sata_uahc_px_sctl_t;
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/**
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* cvmx_sata_uahc_p#_cmd
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*/
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union cvmx_sata_uahc_px_cmd {
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u32 u32;
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struct cvmx_sata_uahc_px_cmd_s {
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u32 icc : 4;
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u32 asp : 1;
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u32 alpe : 1;
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u32 dlae : 1;
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u32 atapi : 1;
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u32 apste : 1;
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u32 fbscp : 1;
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u32 esp : 1;
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u32 cpd : 1;
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u32 mpsp : 1;
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u32 hpcp : 1;
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u32 pma : 1;
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u32 cps : 1;
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u32 cr : 1;
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u32 fr : 1;
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u32 mpss : 1;
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u32 ccs : 5;
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u32 reserved_5_7 : 3;
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u32 fre : 1;
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u32 clo : 1;
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u32 pod : 1;
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u32 sud : 1;
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u32 st : 1;
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} s;
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struct cvmx_sata_uahc_px_cmd_s cn70xx;
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struct cvmx_sata_uahc_px_cmd_s cn70xxp1;
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struct cvmx_sata_uahc_px_cmd_s cn73xx;
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};
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typedef union cvmx_sata_uahc_px_cmd cvmx_sata_uahc_px_cmd_t;
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/**
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* cvmx_sata_uahc_gbl_pi
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*
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* See AHCI specification v1.3 section 3.1.
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*
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*/
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union cvmx_sata_uahc_gbl_pi {
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u32 u32;
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struct cvmx_sata_uahc_gbl_pi_s {
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u32 reserved_2_31 : 30;
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u32 pi : 2;
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} s;
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struct cvmx_sata_uahc_gbl_pi_s cn70xx;
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struct cvmx_sata_uahc_gbl_pi_s cn70xxp1;
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struct cvmx_sata_uahc_gbl_pi_s cn73xx;
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};
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typedef union cvmx_sata_uahc_gbl_pi cvmx_sata_uahc_gbl_pi_t;
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/**
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* cvmx_sata_uahc_p#_ssts
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*/
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union cvmx_sata_uahc_px_ssts {
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u32 u32;
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struct cvmx_sata_uahc_px_ssts_s {
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u32 reserved_12_31 : 20;
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u32 ipm : 4;
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u32 spd : 4;
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u32 det : 4;
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} s;
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struct cvmx_sata_uahc_px_ssts_s cn70xx;
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struct cvmx_sata_uahc_px_ssts_s cn70xxp1;
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struct cvmx_sata_uahc_px_ssts_s cn73xx;
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};
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typedef union cvmx_sata_uahc_px_ssts cvmx_sata_uahc_px_ssts_t;
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/**
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* cvmx_sata_uahc_p#_tfd
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*/
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union cvmx_sata_uahc_px_tfd {
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u32 u32;
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struct cvmx_sata_uahc_px_tfd_s {
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u32 reserved_16_31 : 16;
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u32 tferr : 8;
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u32 sts : 8;
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} s;
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struct cvmx_sata_uahc_px_tfd_s cn70xx;
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struct cvmx_sata_uahc_px_tfd_s cn70xxp1;
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struct cvmx_sata_uahc_px_tfd_s cn73xx;
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};
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typedef union cvmx_sata_uahc_px_tfd cvmx_sata_uahc_px_tfd_t;
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/**
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* cvmx_sata_uahc_gbl_timer1ms
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*/
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union cvmx_sata_uahc_gbl_timer1ms {
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u32 u32;
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struct cvmx_sata_uahc_gbl_timer1ms_s {
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u32 reserved_20_31 : 12;
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u32 timv : 20;
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} s;
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struct cvmx_sata_uahc_gbl_timer1ms_s cn70xx;
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struct cvmx_sata_uahc_gbl_timer1ms_s cn70xxp1;
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struct cvmx_sata_uahc_gbl_timer1ms_s cn73xx;
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};
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typedef union cvmx_sata_uahc_gbl_timer1ms cvmx_sata_uahc_gbl_timer1ms_t;
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#endif
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