mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-18 09:13:06 +00:00
34dec6a443
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 - 2022, Xilinx, Inc.
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*/
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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struct crlapb_regs {
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u32 reserved0[67];
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u32 cpu_r5_ctrl;
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u32 reserved;
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u32 iou_switch_ctrl; /* 0x114 */
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u32 reserved1[13];
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u32 timestamp_ref_ctrl; /* 0x14c */
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u32 reserved3[108];
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u32 rst_cpu_r5;
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u32 reserved2[17];
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u32 rst_timestamp; /* 0x348 */
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};
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struct iou_scntrs_regs {
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u32 counter_control_register; /* 0x0 */
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u32 reserved0[7];
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u32 base_frequency_id_register; /* 0x20 */
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};
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struct crp_regs {
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u32 reserved0[128];
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u32 boot_mode_usr; /* 0x200 */
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};
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#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000
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#define VERSAL_NET_CRP_BASEADDR 0xF1260000
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#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000
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#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
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#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
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#define IOU_SCNTRS_CONTROL_EN 1
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#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
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#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
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#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
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#define PMC_TAP 0xF11A0000
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#define PMC_TAP_IDCODE (PMC_TAP + 0)
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#define PMC_TAP_VERSION (PMC_TAP + 0x4)
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# define PMC_VERSION_MASK GENMASK(7, 0)
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# define PS_VERSION_MASK GENMASK(15, 8)
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# define PS_VERSION_PRODUCTION 0x20
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# define RTL_VERSION_MASK GENMASK(23, 16)
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# define PLATFORM_MASK GENMASK(27, 24)
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# define PLATFORM_VERSION_MASK GENMASK(31, 28)
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#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
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/* Bootmode setting values */
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#define BOOT_MODES_MASK 0x0000000F
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#define QSPI_MODE_24BIT 0x00000001
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#define QSPI_MODE_32BIT 0x00000002
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#define SD_MODE 0x00000003 /* sd 0 */
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#define SD_MODE1 0x00000005 /* sd 1 */
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#define EMMC_MODE 0x00000006
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#define USB_MODE 0x00000007
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#define OSPI_MODE 0x00000008
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#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
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#define JTAG_MODE 0x00000000
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#define BOOT_MODE_USE_ALT 0x100
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#define BOOT_MODE_ALT_SHIFT 12
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enum versal_net_platform {
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VERSAL_NET_SILICON = 0,
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VERSAL_NET_SPP = 1,
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VERSAL_NET_EMU = 2,
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VERSAL_NET_QEMU = 3,
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};
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#define VERSAL_SLCR_BASEADDR 0xF1060000
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#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
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#define VERSAL_OSPI_LINEAR_MODE BIT(1)
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#define FLASH_RESET_GPIO 0xc
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#define WPROT_CRP 0xF126001C
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#define RST_GPIO 0xF1260318
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#define WPROT_LPD_MIO 0xFF080728
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#define WPROT_PMC_MIO 0xF1060828
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#define BOOT_MODE_DIR 0xF1020204
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#define BOOT_MODE_OUT 0xF1020208
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#define MIO_PIN_12 0xF1060030
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#define BANK0_OUTPUT 0xF1020040
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#define BANK0_TRI 0xF1060200
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