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403 lines
14 KiB
C
403 lines
14 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T MBX board.
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* Copied from the FADS stuff, which was originally copied from the MBX stuff!
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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* Rob Taylor coverted it back to MBX
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_MBX 1
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#define CONFIG_8xx_CPUCLOCK 40
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#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK)
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#define TARGET_SYSTEM_FREQUENCY 40
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_BAUDRATE 9600
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 40000000 /* 50 MHz in */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 1
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#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */
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#define CONFIG_8xx_TFTP_MODE
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#else
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#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_8xx_TFTP_MODE
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#endif
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#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */
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#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
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#define CONFIG_BOOTARGS " "
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/*
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* Miscellaneous configurable options
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*/
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#undef CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT ":>" /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFFA00000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
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#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
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#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
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#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
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#define CFG_PCIMEM_OR 0xA0000108
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#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
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#define CFG_PCIBRIDGE_OR 0xFFFF0108
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
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#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
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#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
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/*-----------------------------------------------------------------------
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* Offset in DPMEM where we keep the VPD data
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*/
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#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x00000000
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/*0xFE000000*/
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* NVRAM Configuration
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*
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* Note: the MBX is special because there is already a firmware on this
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* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
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* access the NVRAM at the offset 0x1000.
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*/
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#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
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#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
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#define CFG_ENV_SIZE 0x1000
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*/
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
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#define CFG_SCCR SCCR_TBS
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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/* the other CS:s are determined by looking at parameters in BCSRx */
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#define BCSR_ADDR ((uint) 0xFF010000)
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#define BCSR_SIZE ((uint)(64 * 1024))
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#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
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#define CFG_BR0_PRELIM (0xFE000000 | BR_V )
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/* BCSRx - Board Control and Status Registers */
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#define CFG_OR1_REMAP CFG_OR0_REMAP
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#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4
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#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V )
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/* 9 column SDRAM */
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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#define CFG_MAMR 0x13821000
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/* values according to the manual */
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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#define BCSR0 ((uint) (BCSR_ADDR + 00))
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
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/* FADS bitvalues by Helmut Buchsbaum
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* see MPC8xxADS User's Manual for a proper description
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* of the following structures
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*/
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#define BCSR0_ERB ((uint)0x80000000)
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#define BCSR0_IP ((uint)0x40000000)
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#define BCSR0_BDIS ((uint)0x10000000)
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#define BCSR0_BPS_MASK ((uint)0x0C000000)
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#define BCSR0_ISB_MASK ((uint)0x01800000)
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#define BCSR0_DBGC_MASK ((uint)0x00600000)
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#define BCSR0_DBPC_MASK ((uint)0x00180000)
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#define BCSR0_EBDF_MASK ((uint)0x00060000)
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#define BCSR1_FLASH_EN ((uint)0x80000000)
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#define BCSR1_DRAM_EN ((uint)0x40000000)
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDEN ((uint)0x10000000)
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
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#define BCSR1_BCSR_EN ((uint)0x02000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_SDRAM_EN ((uint)0x00020000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
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#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
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#define BCSR2_DRAM_PD_SHIFT (23)
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#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
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#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
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#define BCSR3_DBID_MASK ((ushort)0x3800)
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#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
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#define BCSR3_BREVNR0 ((ushort)0x0080)
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#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
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#define BCSR3_BREVN1 ((ushort)0x0008)
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#define BCSR3_BREVN2_MASK ((ushort)0x0003)
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#define BCSR4_ETHLOOP ((uint)0x80000000)
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#define BCSR4_TFPLDL ((uint)0x40000000)
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#define BCSR4_TPSQEL ((uint)0x20000000)
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
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#ifdef CONFIG_MPC823
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#define BCSR4_USB_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860SAR
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#define BCSR4_UTOPIA_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860SAR */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860T */
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#define BCSR4_USB_SPEED ((uint)0x04000000)
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#define BCSR4_VCCO ((uint)0x02000000)
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#define BCSR4_VIDEO_ON ((uint)0x00800000)
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#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
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#define BCSR4_VIDEO_RST ((uint)0x00200000)
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#define BCSR4_MODEM_EN ((uint)0x00100000)
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#define CONFIG_DRAM_40MHZ 1
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#ifdef CONFIG_MPC860T
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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#endif /* CONFIG_MPC860T */
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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/*
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* MPC8xx CPM Options
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*/
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#define CONFIG_SCC_ENET 1
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#define CONFIG_SCC1_ENET 1
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#define CONFIG_FEC_ENET 1
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#undef CONFIG_CPM_IIC
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#undef CONFIG_UCODE_PATCH
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#define CONFIG_DISK_SPINUP_TIME 1000000
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/* PCMCIA configuration */
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#define PCMCIA_MAX_SLOTS 2
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#ifdef CONFIG_MPC860
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#define PCMCIA_SLOT_A 1
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#endif
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#endif /* __CONFIG_H */
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