mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 19:43:33 +00:00
504 lines
17 KiB
C
504 lines
17 KiB
C
/*
|
|
* Copyright 2004 Freescale Semiconductor.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <pci.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/immap_85xx.h>
|
|
#include <ioports.h>
|
|
#include <spd.h>
|
|
|
|
#include "../common/cadmus.h"
|
|
#include "../common/eeprom.h"
|
|
#include "../common/via.h"
|
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
|
#endif
|
|
|
|
extern long int spd_sdram(void);
|
|
|
|
void local_bus_init(void);
|
|
void sdram_init(void);
|
|
|
|
/*
|
|
* I/O Port configuration table
|
|
*
|
|
* if conf is 1, then that port pin will be configured at boot time
|
|
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
|
*/
|
|
|
|
const iop_conf_t iop_conf_tab[4][32] = {
|
|
|
|
/* Port A configuration */
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
|
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
|
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
|
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
|
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
|
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
|
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
|
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
|
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
|
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
|
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
|
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
|
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
|
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
|
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
|
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
|
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
|
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
|
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
|
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
|
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
|
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
|
|
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
|
|
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
|
|
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
|
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
|
|
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
|
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
|
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
|
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
|
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
|
|
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
|
},
|
|
|
|
/* Port B configuration */
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
|
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
|
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
|
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
|
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
|
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
|
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
|
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
|
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
|
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
|
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
|
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
|
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
|
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
|
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
|
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
|
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
|
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
|
|
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
|
|
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
|
|
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
|
|
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
|
|
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
|
},
|
|
|
|
/* Port C */
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
|
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
|
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
|
|
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
|
|
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
|
|
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
|
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
|
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
|
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
|
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
|
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
|
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
|
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
|
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
|
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
|
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
|
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
|
|
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
|
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
|
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
|
|
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
|
|
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
|
|
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
|
|
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
|
|
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
|
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
|
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
|
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
|
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
|
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
|
|
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
|
|
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
|
|
},
|
|
|
|
/* Port D */
|
|
{ /* conf ppar psor pdir podr pdat */
|
|
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
|
|
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
|
|
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
|
|
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
|
|
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
|
|
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
|
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
|
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
|
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
|
|
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
|
|
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
|
|
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
|
|
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
|
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
|
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
|
|
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
|
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
|
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
|
|
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
|
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
|
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
|
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
|
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
|
|
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
|
|
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
|
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
|
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
|
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
|
|
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
|
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
|
}
|
|
};
|
|
|
|
int board_early_init_f (void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int checkboard (void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
|
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
|
|
/* PCI slot in USER bits CSR[6:7] by convention. */
|
|
uint pci_slot = get_pci_slot ();
|
|
|
|
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
|
|
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
|
|
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
|
|
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
|
|
|
|
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
|
|
|
|
uint cpu_board_rev = get_cpu_board_revision ();
|
|
|
|
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
|
|
get_board_version (), pci_slot);
|
|
|
|
printf ("CPU Board Revision %d.%d (0x%04x)\n",
|
|
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
|
|
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
|
|
|
|
printf (" PCI1: %d bit, %s MHz, %s\n",
|
|
(pci1_32) ? 32 : 64,
|
|
(pci1_speed == 33000000) ? "33" :
|
|
(pci1_speed == 66000000) ? "66" : "unknown",
|
|
pci1_clk_sel ? "sync" : "async");
|
|
|
|
if (pci_dual) {
|
|
printf (" PCI2: 32 bit, 66 MHz, %s\n",
|
|
pci2_clk_sel ? "sync" : "async");
|
|
} else {
|
|
printf (" PCI2: disabled\n");
|
|
}
|
|
|
|
/*
|
|
* Initialize local bus.
|
|
*/
|
|
local_bus_init ();
|
|
|
|
return 0;
|
|
}
|
|
|
|
long int
|
|
initdram(int board_type)
|
|
{
|
|
long dram_size = 0;
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
|
|
puts("Initializing\n");
|
|
|
|
#if defined(CONFIG_DDR_DLL)
|
|
{
|
|
/*
|
|
* Work around to stabilize DDR DLL MSYNC_IN.
|
|
* Errata DDR9 seems to have been fixed.
|
|
* This is now the workaround for Errata DDR11:
|
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
|
*/
|
|
|
|
volatile ccsr_gur_t *gur= &immap->im_gur;
|
|
|
|
gur->ddrdllcr = 0x81000000;
|
|
asm("sync;isync;msync");
|
|
udelay(200);
|
|
}
|
|
#endif
|
|
dram_size = spd_sdram();
|
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
|
/*
|
|
* Initialize and enable DDR ECC.
|
|
*/
|
|
ddr_enable_ecc(dram_size);
|
|
#endif
|
|
/*
|
|
* SDRAM Initialization
|
|
*/
|
|
sdram_init();
|
|
|
|
puts(" DDR: ");
|
|
return dram_size;
|
|
}
|
|
|
|
/*
|
|
* Initialize Local Bus
|
|
*/
|
|
void
|
|
local_bus_init(void)
|
|
{
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
|
|
uint clkdiv;
|
|
uint lbc_hz;
|
|
sys_info_t sysinfo;
|
|
uint temp_lbcdll;
|
|
|
|
/*
|
|
* Errata LBC11.
|
|
* Fix Local Bus clock glitch when DLL is enabled.
|
|
*
|
|
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
|
|
* If localbus freq is > 133Mhz, DLL can be safely enabled.
|
|
* Between 66 and 133, the DLL is enabled with an override workaround.
|
|
*/
|
|
|
|
get_sys_info(&sysinfo);
|
|
clkdiv = lbc->lcrr & 0x0f;
|
|
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
|
|
|
|
if (lbc_hz < 66) {
|
|
lbc->lcrr |= 0x80000000; /* DLL Bypass */
|
|
|
|
} else if (lbc_hz >= 133) {
|
|
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
|
|
|
|
} else {
|
|
lbc->lcrr &= (~0x8000000); /* DLL Enabled */
|
|
udelay(200);
|
|
|
|
/*
|
|
* Sample LBC DLL ctrl reg, upshift it to set the
|
|
* override bits.
|
|
*/
|
|
temp_lbcdll = gur->lbcdllcr;
|
|
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
|
asm("sync;isync;msync");
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Initialize SDRAM memory on the Local Bus.
|
|
*/
|
|
void
|
|
sdram_init(void)
|
|
{
|
|
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
|
|
|
uint idx;
|
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
|
uint cpu_board_rev;
|
|
uint lsdmr_common;
|
|
|
|
puts(" SDRAM: ");
|
|
|
|
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
|
|
|
|
/*
|
|
* Setup SDRAM Base and Option Registers
|
|
*/
|
|
lbc->or2 = CFG_OR2_PRELIM;
|
|
asm("msync");
|
|
|
|
lbc->br2 = CFG_BR2_PRELIM;
|
|
asm("msync");
|
|
|
|
lbc->lbcr = CFG_LBC_LBCR;
|
|
asm("msync");
|
|
|
|
lbc->lsrt = CFG_LBC_LSRT;
|
|
lbc->mrtpr = CFG_LBC_MRTPR;
|
|
asm("msync");
|
|
|
|
/*
|
|
* Determine which address lines to use baed on CPU board rev.
|
|
*/
|
|
cpu_board_rev = get_cpu_board_revision();
|
|
lsdmr_common = CFG_LBC_LSDMR_COMMON;
|
|
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
|
|
lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
|
|
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
|
|
lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
|
|
} else {
|
|
/*
|
|
* Assume something unable to identify itself is
|
|
* really old, and likely has lines 16/17 mapped.
|
|
*/
|
|
lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
|
|
}
|
|
|
|
/*
|
|
* Issue PRECHARGE ALL command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
|
|
/*
|
|
* Issue 8 AUTO REFRESH commands.
|
|
*/
|
|
for (idx = 0; idx < 8; idx++) {
|
|
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
}
|
|
|
|
/*
|
|
* Issue 8 MODE-set command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(100);
|
|
|
|
/*
|
|
* Issue NORMAL OP command.
|
|
*/
|
|
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
|
|
asm("sync;msync");
|
|
*sdram_addr = 0xff;
|
|
ppcDcbf((unsigned long) sdram_addr);
|
|
udelay(200); /* Overkill. Must wait > 200 bus cycles */
|
|
|
|
#endif /* enable SDRAM init */
|
|
}
|
|
|
|
#if defined(CFG_DRAM_TEST)
|
|
int
|
|
testdram(void)
|
|
{
|
|
uint *pstart = (uint *) CFG_MEMTEST_START;
|
|
uint *pend = (uint *) CFG_MEMTEST_END;
|
|
uint *p;
|
|
|
|
printf("Testing DRAM from 0x%08x to 0x%08x\n",
|
|
CFG_MEMTEST_START,
|
|
CFG_MEMTEST_END);
|
|
|
|
printf("DRAM test phase 1:\n");
|
|
for (p = pstart; p < pend; p++)
|
|
*p = 0xaaaaaaaa;
|
|
|
|
for (p = pstart; p < pend; p++) {
|
|
if (*p != 0xaaaaaaaa) {
|
|
printf ("DRAM test fails at: %08x\n", (uint) p);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
printf("DRAM test phase 2:\n");
|
|
for (p = pstart; p < pend; p++)
|
|
*p = 0x55555555;
|
|
|
|
for (p = pstart; p < pend; p++) {
|
|
if (*p != 0x55555555) {
|
|
printf ("DRAM test fails at: %08x\n", (uint) p);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
printf("DRAM test passed.\n");
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI
|
|
/* For some reason the Tundra PCI bridge shows up on itself as a
|
|
* different device. Work around that by refusing to configure it
|
|
*/
|
|
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
|
|
|
|
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
|
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
|
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
|
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
|
|
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
|
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
|
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
|
|
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
|
|
};
|
|
|
|
|
|
static struct pci_controller hose[] = {
|
|
{
|
|
config_table: pci_mpc85xxcds_config_table,
|
|
},
|
|
#ifdef CONFIG_MPC85XX_PCI2
|
|
{ }
|
|
#endif
|
|
};
|
|
|
|
#endif
|
|
|
|
void
|
|
pci_init_board(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
extern void pci_mpc85xx_init(struct pci_controller *hose);
|
|
|
|
pci_mpc85xx_init(hose);
|
|
#endif
|
|
}
|