mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
a257f6263b
On a real Malta the Super I/O needs to be configured before we are able to access the UARTs. This patch performs that configuration, setting up the UARTs in the same way that YAMON would. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
63 lines
1.3 KiB
C
63 lines
1.3 KiB
C
/*
|
|
* Copyright (C) 2013 Imagination Technologies
|
|
* Author: Paul Burton <paul.burton@imgtec.com>
|
|
*
|
|
* Setup code for the FDC37M817 super I/O controller
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
|
|
#define SIO_CONF_PORT 0x3f0
|
|
#define SIO_DATA_PORT 0x3f1
|
|
|
|
enum sio_conf_key {
|
|
SIOCONF_DEVNUM = 0x07,
|
|
SIOCONF_ACTIVATE = 0x30,
|
|
SIOCONF_ENTER_SETUP = 0x55,
|
|
SIOCONF_BASE_HIGH = 0x60,
|
|
SIOCONF_BASE_LOW = 0x61,
|
|
SIOCONF_PRIMARY_INT = 0x70,
|
|
SIOCONF_EXIT_SETUP = 0xaa,
|
|
SIOCONF_MODE = 0xf0,
|
|
};
|
|
|
|
static struct {
|
|
u8 key;
|
|
u8 data;
|
|
} sio_config[] = {
|
|
/* tty0 */
|
|
{ SIOCONF_DEVNUM, 0x04 },
|
|
{ SIOCONF_BASE_HIGH, 0x03 },
|
|
{ SIOCONF_BASE_LOW, 0xf8 },
|
|
{ SIOCONF_MODE, 0x02 },
|
|
{ SIOCONF_PRIMARY_INT, 0x04 },
|
|
{ SIOCONF_ACTIVATE, 0x01 },
|
|
|
|
/* tty1 */
|
|
{ SIOCONF_DEVNUM, 0x05 },
|
|
{ SIOCONF_BASE_HIGH, 0x02 },
|
|
{ SIOCONF_BASE_LOW, 0xf8 },
|
|
{ SIOCONF_MODE, 0x02 },
|
|
{ SIOCONF_PRIMARY_INT, 0x03 },
|
|
{ SIOCONF_ACTIVATE, 0x01 },
|
|
};
|
|
|
|
void malta_superio_init(void *io_base)
|
|
{
|
|
unsigned i;
|
|
|
|
/* enter config state */
|
|
writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
|
|
|
|
/* configure peripherals */
|
|
for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
|
|
writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
|
|
writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
|
|
}
|
|
|
|
/* exit config state */
|
|
writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
|
|
}
|