Bin Meng 142dd57c5d riscv: dts: hifive-unleashed-a00: Make memory node available to SPL ... Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>		2020-07-24 14:56:29 +08:00
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ae350_32.dts	riscv: dts: Add #address-cells and #size-cells in nor node	2019-12-10 08:23:10 +08:00
ae350_64.dts	riscv: dts: Add #address-cells and #size-cells in nor node	2019-12-10 08:23:10 +08:00
fu540-c000-u-boot.dtsi	riscv: sifive: fu540: enable all cache ways from U-Boot proper	2020-07-03 15:09:06 +08:00
fu540-c000.dtsi	riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux	2020-06-04 09:44:09 +08:00
fu540-hifive-unleashed-a00-ddr.dtsi	sifive: dts: fu540: Add DDR controller and phy register settings	2020-06-04 09:44:08 +08:00
hifive-unleashed-a00-u-boot.dtsi	riscv: dts: hifive-unleashed-a00: Make memory node available to SPL	2020-07-24 14:56:29 +08:00
hifive-unleashed-a00.dts	riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux	2020-06-04 09:44:09 +08:00
k210-maix-bit.dts	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00
k210.dtsi	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00
Makefile	riscv: Add device tree for K210 and Sipeed Maix BitM	2020-07-01 15:01:22 +08:00