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https://github.com/AsahiLinux/u-boot
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e75cc00982
This patch adds a clock driver for MediaTek MT7621 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MT7621_CLK_H_
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#define _DT_BINDINGS_MT7621_CLK_H_
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#define MT7621_CLK_XTAL 0
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#define MT7621_CLK_CPU 1
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#define MT7621_CLK_BUS 2
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#define MT7621_CLK_50M 3
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#define MT7621_CLK_125M 4
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#define MT7621_CLK_150M 5
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#define MT7621_CLK_250M 6
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#define MT7621_CLK_270M 7
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#define MT7621_CLK_HSDMA 8
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#define MT7621_CLK_FE 9
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#define MT7621_CLK_SP_DIVTX 10
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#define MT7621_CLK_TIMER 11
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#define MT7621_CLK_PCM 12
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#define MT7621_CLK_PIO 13
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#define MT7621_CLK_GDMA 14
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#define MT7621_CLK_NAND 15
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#define MT7621_CLK_I2C 16
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#define MT7621_CLK_I2S 17
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#define MT7621_CLK_SPI 18
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#define MT7621_CLK_UART1 19
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#define MT7621_CLK_UART2 20
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#define MT7621_CLK_UART3 21
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#define MT7621_CLK_ETH 22
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#define MT7621_CLK_PCIE0 23
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#define MT7621_CLK_PCIE1 24
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#define MT7621_CLK_PCIE2 25
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#define MT7621_CLK_CRYPTO 26
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#define MT7621_CLK_SHXC 27
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#define MT7621_CLK_MAX 28
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/* for u-boot only */
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#define MT7621_CLK_DDR 29
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#endif /* _DT_BINDINGS_MT7621_CLK_H_ */
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