u-boot/drivers/watchdog/ulp_wdog.c
Harald Seiler 35b65dd8ef reset: Remove addr parameter from reset_cpu()
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-02 14:03:02 -05:00

96 lines
2.1 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* MX7ULP WDOG Register Map
*/
struct wdog_regs {
u8 cs1;
u8 cs2;
u16 reserve0;
u32 cnt;
u32 toval;
u32 win;
};
#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
#endif
#define REFRESH_WORD0 0xA602 /* 1st refresh word */
#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
#define WDGCS1_WDGE (1<<7)
#define WDGCS1_WDGUPDATE (1<<5)
#define WDGCS2_FLG (1<<6)
#define WDG_BUS_CLK (0x0)
#define WDG_LPO_CLK (0x1)
#define WDG_32KHZ_CLK (0x2)
#define WDG_EXT_CLK (0x3)
void hw_watchdog_set_timeout(u16 val)
{
/* setting timeout value */
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
writel(val, &wdog->toval);
}
void hw_watchdog_reset(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
writel(REFRESH_WORD0, &wdog->cnt);
writel(REFRESH_WORD1, &wdog->cnt);
}
void hw_watchdog_init(void)
{
u8 val;
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
writel(UNLOCK_WORD0, &wdog->cnt);
writel(UNLOCK_WORD1, &wdog->cnt);
val = readb(&wdog->cs2);
val |= WDGCS2_FLG;
writeb(val, &wdog->cs2);
hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
writel(0, &wdog->win);
writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
hw_watchdog_reset();
}
void reset_cpu(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
writel(UNLOCK_WORD0, &wdog->cnt);
writel(UNLOCK_WORD1, &wdog->cnt);
hw_watchdog_set_timeout(5); /* 5ms timeout */
writel(0, &wdog->win);
writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
hw_watchdog_reset();
while (1);
}