mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/*
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* (C) Copyright 2002 ELTEC Elektronik AG
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* Frank Gottschling <fgottschling@eltec.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* PCI initialisation for the MPC10x.
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*/
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#include <common.h>
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#include <pci.h>
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#include <mpc106.h>
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#ifdef CONFIG_PCI
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struct pci_controller local_hose;
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void pci_init_board(void)
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{
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struct pci_controller* hose = (struct pci_controller *)&local_hose;
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u32 reg32;
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u16 reg16;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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/*
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* Attention: pci_hose_phys_to_bus() failes in address compare,
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* so we need (CFG_PCI_MEMORY_SIZE-1)
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*/
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CFG_PCI_MEMORY_SIZE-1,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI_MEM_BUS,
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CFG_PCI_MEM_PHYS,
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CFG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* ISA/PCI memory space */
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pci_set_region(hose->regions + 2,
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CFG_ISA_MEM_BUS,
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CFG_ISA_MEM_PHYS,
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CFG_ISA_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 3,
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CFG_PCI_IO_BUS,
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CFG_PCI_IO_PHYS,
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CFG_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* ISA/PCI I/O space */
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pci_set_region(hose->regions + 4,
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CFG_ISA_IO_BUS,
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CFG_ISA_IO_PHYS,
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CFG_ISA_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 5;
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pci_setup_indirect(hose,
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MPC106_REG_ADDR,
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MPC106_REG_DATA);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* Initialises the MPC10x PCI Configuration regs. */
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pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, ®32);
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reg32 |= PICR2_CF_SNOOP_WS(3) |
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PICR2_CF_FLUSH_L2 |
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PICR2_CF_L2_HIT_DELAY(3) |
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PICR2_CF_APHASE_WS(3);
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reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
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pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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/* Clear non-reserved bits in status register */
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pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, ®32);
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reg32 |= PICR1_CF_CBA(63) |
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PICR1_CF_BREAD_WS(2) |
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PICR1_MCP_EN |
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PICR1_CF_DPARK |
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PICR1_PROC_TYPE_604 |
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PICR1_CF_LOOP_SNOOP |
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PICR1_CF_APARK;
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pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
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}
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#endif /* CONFIG_PCI */
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