mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
156 lines
2.6 KiB
ArmAsm
156 lines
2.6 KiB
ArmAsm
#include "macros.h"
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#define GLOBALINFO0 0x50
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#define GLOBALINFO0_BO (1<<7)
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#define GLOBALINFO2_B1ARBITER (1<<6)
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#define HBUSACR0 0x5c
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#define HBUSACR2_BURST (1<<0)
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#define HBUSACR2_LAT (1<<1)
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#define RECEIVER_HOLDING 0
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#define TRANSMITTER_HOLDING 0
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#define INTERRUPT_ENABLE 1
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#define INTERRUPT_STATUS 2
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#define FIFO_CONTROL 2
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#define LINE_CONTROL 3
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#define MODEM_CONTROL 4
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#define LINE_STATUS 5
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#define MODEM_STATUS 6
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#define SCRATCH_PAD 7
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#define DIVISOR_LATCH_LSB 0
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#define DIVISOR_LATCH_MSB 1
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#define PRESCALER_DIVISION 5
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#define UART(x) (0x3f8+(x))
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#define GLOBALINFO0 0x50
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#define GLOBALINFO0_BO (1<<7)
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#define GLOBALINFO2_B1ARBITER (1<<6)
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#define HBUSACR0 0x5c
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#define HBUSACR2_BURST (1<<0)
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#define HBUSACR2_LAT (1<<1)
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#define SUPERIO_1 ((7 << 3) | (0))
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#define SUPERIO_2 ((7 << 3) | (1))
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.globl board_asm_init
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board_asm_init:
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mflr r29
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/* Set 'Must-set' register */
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li r3, 0
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li r4, 0
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li r5, 0x5e
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bl pci_read_cfg_byte
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ori r3, r3, (1<<1)
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xori r6, r3, (1<<1)
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li r3, 0
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bl pci_write_cfg_byte
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li r3, 0
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li r5, 0x52
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bl pci_read_cfg_byte
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ori r6, r3, (1<<6)
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li r3, 0
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bl pci_write_cfg_byte
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li r3, 0
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li r4, 0x08
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li r5, 0xd2
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bl pci_read_cfg_byte
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ori r6, r3, (1<<2)
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li r3, 0
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bl pci_write_cfg_byte
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/* Do PCI reset */
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/* li r3, 0
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li r4, 0x38
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li r5, 0x47
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bl pci_read_cfg_byte
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ori r6, r3, 0x01
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li r3, 0
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li r4, 0x38
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li r5, 0x47
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bl pci_write_cfg_byte*/
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/* Enable NVRAM for environment */
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li r3, 0
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li r4, 0
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li r5, 0x56
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li r6, 0x0B
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bl pci_write_cfg_byte
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/* Init Super-I/O chips */
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siowb 0x40, 0x08
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siowb 0x41, 0x01
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siowb 0x45, 0x80
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siowb 0x46, 0x60
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siowb 0x47, 0x20
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siowb 0x48, 0x01
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siowb 0x4a, 0xc4
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siowb 0x50, 0x0e
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siowb 0x51, 0x76
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siowb 0x52, 0x34
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siowb 0x54, 0x00
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siowb 0x55, 0x90
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siowb 0x56, 0x99
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siowb 0x57, 0x90
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siowb 0x85, 0x01
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/* Enable configuration mode for SuperIO */
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li r3, 0
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li r4, (7<<3)
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li r5, 0x85
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bl pci_read_cfg_byte
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ori r6, r3, 0x02
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mr r31, r6
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li r3,0
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bl pci_write_cfg_byte
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/* COM1 as 3f8 */
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outb 0x3f0, 0xe7
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outb 0x3f1, 0xfe
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/* COM2 as 2f8 */
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outb 0x3f0, 0xe8
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outb 0x3f1, 0xeb
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/* Enable */
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outb 0x3f0, 0xe2
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inb r3, 0x3f1
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ori r3, r3, 0x0c
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outb 0x3f0, 0xe2
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outbr 0x3f1, r3
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/* Disable configuration mode */
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li r3, 0
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li r4, (7<<3)
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li r5, 0x85
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mr r6, r31
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bl pci_write_cfg_byte
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/* Set line control */
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outb UART(LINE_CONTROL), 0x83
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outb UART(DIVISOR_LATCH_LSB), 0x0c
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outb UART(DIVISOR_LATCH_MSB), 0x00
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outb UART(LINE_CONTROL), 0x3
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mtlr r29
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blr
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.globl new_reset
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.globl new_reset_end
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new_reset:
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li r0, 0x100
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oris r0, r0, 0xFFF0
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mtlr r0
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blr
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new_reset_end:
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