mirror of
https://github.com/AsahiLinux/u-boot
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323 lines
13 KiB
C
323 lines
13 KiB
C
/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_405EP 1 /* this is a PPC405 CPU */
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#define CONFIG_4xx 1 /* member of PPC4xx family */
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#define CONFIG_TAIHU 1 /* on a taihu board */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME taihu
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_NO_SERIAL_EEPROM
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/*----------------------------------------------------------------------------*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*
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!-------------------------------------------------------------------------------
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! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
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! assuming a 33MHz input clock to the 405EP from the C9531.
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!-------------------------------------------------------------------------------
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*/
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#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_3)
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#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
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#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_1)
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#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
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#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
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#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
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#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
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#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
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#endif
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/*----------------------------------------------------------------------------*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_PPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC180000\0" \
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""
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#define CONFIG_PHY_ADDR 0x14 /* PHY address */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
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#define CONFIG_PHY_RESET 1
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SPI
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#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
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#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
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#define CONFIG_SYS_SDRAM_BANKS 2
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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*/
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
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/* SDRAM timings used in datasheet */
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
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/*
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_UART1_CONSOLE 1
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/*-----------------------------------------------------------------------
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* I2C stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CONFIG_SOFT_SPI
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#define SPI_SCL spi_scl
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#define SPI_SDA spi_sda
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#define SPI_READ spi_read()
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#define SPI_DELAY udelay(2)
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#ifndef __ASSEMBLY__
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void spi_scl(int);
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void spi_sda(int);
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unsigned char spi_read(void);
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#endif
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/* standard dtt sensor configuration */
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#define CONFIG_DTT_DS1775 1
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#define CONFIG_DTT_SENSORS { 0 }
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#define CONFIG_SYS_I2C_DTT_ADDR 0x49
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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#define CONFIG_EEPRO100 1
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFFE00000
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_ADDR0 0x555
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#define CONFIG_SYS_FLASH_ADDR1 0x2aa
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
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#endif
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/*-----------------------------------------------------------------------
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* PPC405 GPIO Configuration
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*/
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
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{ \
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/* GPIO Core 0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
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} \
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}
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory (OCM) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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/* Memory Bank 0 (Flash/SRAM) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x03815600
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#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x05815600
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#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
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/* Memory Bank 2 (USB device) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x03016600
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#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 3 (LCM and D-flip-flop) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x158FF600
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#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 4 (not install) initialization */
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#define CONFIG_SYS_EBC_PB4AP 0x158FF600
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#define CONFIG_SYS_EBC_PB4CR 0x5021A000
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#define CPLD_REG0_ADDR 0x50100000
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#define CPLD_REG1_ADDR 0x50100001
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#endif /* __CONFIG_H */
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