mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 14:40:41 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
401 lines
10 KiB
C
401 lines
10 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <asm/arch/clock.h>
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#include <linux/errno.h>
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#include <asm/imx-common/mx5_video.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#include <power/pmic.h>
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#include <dialog_pmic.h>
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#include <fsl_pmic.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
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DECLARE_GLOBAL_DATA_PTR;
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static uint32_t mx53_dram_size[2];
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phys_size_t get_effective_memsize(void)
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{
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/*
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* WARNING: We must override get_effective_memsize() function here
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* to report only the size of the first DRAM bank. This is to make
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* U-Boot relocator place U-Boot into valid memory, that is, at the
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* end of the first DRAM bank. If we did not override this function
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* like so, U-Boot would be placed at the address of the first DRAM
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* bank + total DRAM size - sizeof(uboot), which in the setup where
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* each DRAM bank contains 512MiB of DRAM would result in placing
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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return mx53_dram_size[0];
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}
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int dram_init(void)
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{
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mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = mx53_dram_size[0];
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = mx53_dram_size[1];
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}
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u32 get_board_rev(void)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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int rev = readl(&fuse->gp[6]);
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if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
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rev = 0;
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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/* request VBUS power enable pin, GPIO7_8 */
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imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
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gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC3_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
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gpio_direction_input(IMX_GPIO_NR(3, 11));
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imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
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gpio_direction_input(IMX_GPIO_NR(3, 13));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
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return ret;
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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MX53_PAD_EIM_DA13__GPIO3_13,
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
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SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
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MX53_PAD_EIM_DA11__GPIO3_11,
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
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}
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static int power_init(void)
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{
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unsigned int val;
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int ret;
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struct pmic *p;
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if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
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ret = pmic_dialog_init(I2C_PMIC);
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if (ret)
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return ret;
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p = pmic_get("DIALOG_PMIC");
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if (!p)
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return -ENODEV;
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setenv("fdt_file", "imx53-qsb.dtb");
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/* Set VDDA to 1.25V */
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val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
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ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
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if (ret) {
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printf("Writing to BUCKCORE_REG failed: %d\n", ret);
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return ret;
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}
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pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
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val |= DA9052_SUPPLY_VBCOREGO;
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ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
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if (ret) {
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printf("Writing to SUPPLY_REG failed: %d\n", ret);
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return ret;
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}
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/* Set Vcc peripheral to 1.30V */
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ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
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if (ret) {
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printf("Writing to BUCKPRO_REG failed: %d\n", ret);
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return ret;
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}
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ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
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if (ret) {
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printf("Writing to SUPPLY_REG failed: %d\n", ret);
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return ret;
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}
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return ret;
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}
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if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
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ret = pmic_init(I2C_0);
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if (ret)
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return ret;
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p = pmic_get("FSL_PMIC");
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if (!p)
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return -ENODEV;
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setenv("fdt_file", "imx53-qsrb.dtb");
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/* Set VDDGP to 1.25V for 1GHz on SW1 */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
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ret = pmic_reg_write(p, REG_SW_0, val);
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if (ret) {
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printf("Writing to REG_SW_0 failed: %d\n", ret);
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return ret;
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}
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/* Set VCC as 1.30V on SW2 */
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pmic_reg_read(p, REG_SW_1, &val);
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val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
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ret = pmic_reg_write(p, REG_SW_1, val);
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if (ret) {
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printf("Writing to REG_SW_1 failed: %d\n", ret);
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return ret;
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}
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/* Set global reset timer to 4s */
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pmic_reg_read(p, REG_POWER_CTL2, &val);
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val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
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ret = pmic_reg_write(p, REG_POWER_CTL2, val);
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if (ret) {
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printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
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return ret;
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}
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/* Set VUSBSEL and VUSBEN for USB PHY supply*/
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pmic_reg_read(p, REG_MODE_0, &val);
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val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
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ret = pmic_reg_write(p, REG_MODE_0, val);
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if (ret) {
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printf("Writing to REG_MODE_0 failed: %d\n", ret);
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return ret;
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}
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/* Set SWBST to 5V in auto mode */
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val = SWBST_AUTO;
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ret = pmic_reg_write(p, SWBST_CTRL, val);
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if (ret) {
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printf("Writing to SWBST_CTRL failed: %d\n", ret);
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return ret;
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}
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return ret;
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}
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return -1;
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}
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static void clock_1GHz(void)
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{
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int ret;
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u32 ref_clk = MXC_HCLK;
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/*
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* After increasing voltage to 1.25V, we can switch
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* CPU clock to 1GHz and DDR to 400MHz safely
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*/
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ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
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if (ret)
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printf("CPU: Switch CPU clock to 1GHZ failed\n");
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ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
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ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
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if (ret)
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printf("CPU: Switch DDR clock to 400MHz failed\n");
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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setup_iomux_lcd();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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mxc_set_sata_internal_clock();
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setup_iomux_i2c();
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return 0;
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}
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int board_late_init(void)
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{
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if (!power_init())
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clock_1GHz();
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: MX53 LOCO\n");
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return 0;
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}
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