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https://github.com/AsahiLinux/u-boot
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063c12633d
This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
346 lines
8.5 KiB
C
346 lines
8.5 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include "../common/ngpixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(&gur->pmuxcr, 0x1000);
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/* Read back the register to synchronize the write. */
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in_be32(&gur->pmuxcr);
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/* Set the pin muxing to enable ETSEC2. */
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clrbits_be32(&gur->pmuxcr2, 0x001F8000);
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return 0;
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}
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int checkboard(void)
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{
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u8 sw;
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puts("Board: P1022DS ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
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sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
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switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
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case 0:
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printf ("vBank: %u\n", ((sw & 0x30) >> 4));
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break;
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case 1:
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printf ("NAND\n");
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break;
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case 2:
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case 3:
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puts ("Promjet\n");
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break;
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}
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return 0;
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}
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#define CONFIG_TFP410_I2C_ADDR 0x38
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/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
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#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
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#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
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/* Route the I2C1 pins to the SSI port instead. */
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#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
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/* Choose the 12.288Mhz codec reference clock */
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#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
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/* Choose the 11.2896Mhz codec reference clock */
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#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
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/* Connect to USB2 */
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#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
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/* Connect to TFM bus */
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#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
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/* Connect to SPI */
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#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
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int misc_init_r(void)
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{
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u8 temp;
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const char *audclk;
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size_t arglen;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* For DVI, enable the TFP410 Encoder. */
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temp = 0xBF;
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if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
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return -1;
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if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
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return -1;
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debug("DVI Encoder Read: 0x%02x\n", temp);
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temp = 0x10;
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if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
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return -1;
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if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
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return -1;
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debug("DVI Encoder Read: 0x%02x\n",temp);
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/* Enable the USB2 in PMUXCR2 and FGPA */
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if (hwconfig("usb2")) {
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clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
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MPC85xx_PMUXCR2_USB);
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setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
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}
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/* tdm and audio can not enable simultaneous*/
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if (hwconfig("tdm") && hwconfig("audclk")){
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printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
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return -1;
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}
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/* Enable the TDM in PMUXCR and FGPA */
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if (hwconfig("tdm")) {
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clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
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MPC85xx_PMUXCR_TDM);
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setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
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/* TDM need some configration option by SPI */
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clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
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MPC85xx_PMUXCR_SPI);
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setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
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}
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/*
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* Enable the reference clock for the WM8776 codec, and route the MUX
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* pins for SSI. The default is the 12.288 MHz clock
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*/
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if (hwconfig("audclk")) {
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temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
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CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
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temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
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audclk = hwconfig_arg("audclk", &arglen);
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/* Check the first two chars only */
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if (audclk && (strncmp(audclk, "11", 2) == 0))
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temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
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else
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temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
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setbits_8(&pixis->brdcfg1, temp);
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}
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return 0;
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}
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/*
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* A list of PCI and SATA slots
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*/
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enum slot_id {
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SLOT_PCIE1 = 1,
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SLOT_PCIE2,
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SLOT_PCIE3,
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SLOT_PCIE4,
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SLOT_PCIE5,
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SLOT_SATA1,
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SLOT_SATA2
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};
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/*
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* This array maps the slot identifiers to their names on the P1022DS board.
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*/
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static const char *slot_names[] = {
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[SLOT_PCIE1] = "Slot 1",
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[SLOT_PCIE2] = "Slot 2",
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[SLOT_PCIE3] = "Slot 3",
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[SLOT_PCIE4] = "Slot 4",
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[SLOT_PCIE5] = "Mini-PCIe",
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[SLOT_SATA1] = "SATA 1",
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[SLOT_SATA2] = "SATA 2",
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};
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/*
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* This array maps a given SERDES configuration and SERDES device to the PCI or
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* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
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*/
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static u8 serdes_dev_slot[][SATA2 + 1] = {
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[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
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[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
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[PCIE2] = SLOT_PCIE5 },
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[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3 },
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[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1c] = { [PCIE1] = SLOT_PCIE1,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
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[0x1f] = { [PCIE1] = SLOT_PCIE1 },
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};
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/*
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* Returns the name of the slot to which the PCIe or SATA controller is
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* connected
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*/
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const char *board_serdes_name(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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enum slot_id slot = serdes_dev_slot[srds_cfg][device];
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const char *name = slot_names[slot];
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if (name)
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return name;
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else
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return "Nothing";
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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return 0;
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}
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/*
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* Initialize on-board and/or PCI Ethernet devices
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*
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* Returns:
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* <0, error
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* 0, no ethernet devices found
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* >0, number of ethernet devices initialized
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*/
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[2];
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unsigned int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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/**
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* ft_codec_setup - fix up the clock-frequency property of the codec node
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*
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* Update the clock-frequency property based on the value of the 'audclk'
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* hwconfig option. If audclk is not specified, then default to 12.288MHz.
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*/
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static void ft_codec_setup(void *blob, const char *compatible)
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{
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const char *audclk;
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size_t arglen;
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u32 freq;
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audclk = hwconfig_arg("audclk", &arglen);
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if (audclk && (strncmp(audclk, "11", 2) == 0))
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freq = 11289600;
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else
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freq = 12288000;
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do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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FT_FSL_PCI_SETUP;
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_fdt_fixup(blob);
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#endif
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/* Update the WM8776 node's clock frequency property */
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ft_codec_setup(blob, "wlf,wm8776");
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}
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#endif
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