mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 23:47:24 +00:00
7202af927b
Transition to the IOPAD macros as used in Linux in which the pin mux mode is specified using a dedicated parameter while also dropping the related MUX_MODEx macros that are no longer needed. This transition will allow us to keep both Linux and U-Boot DTS in sync more easily. While at it also align the file name of the include file itself and update any references accordingly. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
214 lines
5.1 KiB
Text
214 lines
5.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/dma/k3-udma.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aliases {
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serial2 = &main_uart0;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c000 0x0 0x2e4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_pmx1: pinmux@11c2e8 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c2e8 0x0 0x24>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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sdhci0: sdhci@04F80000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x0 0x4F80000 0x0 0x1000>,
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<0x0 0x4F90000 0x0 0x400>;
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clocks = <&k3_clks 47 1>;
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power-domains = <&k3_pds 47>;
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max-frequency = <25000000>;
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};
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sdhci1: sdhci@04FA0000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x0 0x4FA0000 0x0 0x1000>,
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<0x0 0x4FB0000 0x0 0x400>;
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clocks = <&k3_clks 48 1>;
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power-domains = <&k3_pds 48>;
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max-frequency = <25000000>;
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};
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};
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&cbass_mcu {
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u-boot,dm-spl;
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0x4301c000 0x0 0x118>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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navss_mcu: navss-mcu {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ti,sci-dev-id = <119>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos",
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"proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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};
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mcu_udmap: udmap@285c0000 {
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compatible = "ti,k3-navss-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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#dma-cells = <3>;
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ti,ringacc = <&mcu_ringacc>;
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ti,psil-base = <0x6000>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <194>;
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ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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<0x2>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
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<0x4>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
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dma-coherent;
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};
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};
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};
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&cbass_wakeup {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main_uart0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
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AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
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AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
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AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
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>;
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u-boot,dm-spl;
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};
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main_mmc0_pins_default: main_mmc0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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u-boot,dm-spl;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
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AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
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AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
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AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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u-boot,dm-spl;
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};
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};
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&main_pmx1 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&sdhci0 {
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u-boot,dm-spl;
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status = "okay";
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non-removable;
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bus-width = <8>;
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc0_pins_default>;
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};
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&sdhci1 {
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u-boot,dm-spl;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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sdhci-caps-mask = <0x7 0x0>;
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};
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