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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
125 lines
4.1 KiB
C
125 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the esd TASREG board.
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*
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* (C) Copyright 2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5249EVB_H
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#define _M5249EVB_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CFG_SYS_UART_PORT (0)
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#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
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/*
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* Clock configuration: enable only one of the following options
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*/
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#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
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#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
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#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
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#define CFG_SYS_MBAR2 0x80000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_SYS_INIT_RAM_ADDR 0x20000000
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#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text);
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SYS_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
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#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
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#if 0 /* test-only */
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#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#ifdef CONFIG_SYS_FLASH_CFI
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# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
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# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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CFG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
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CFG_SYS_INIT_RAM_SIZE - 4)
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#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
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#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
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CF_ADDRMASK(2) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
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CF_CACR_DBWE)
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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/* CS0 - AMD Flash, address 0xffc00000 */
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#define CFG_SYS_CS0_BASE 0xffe00000
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#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
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/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
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#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
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/* CS1 - FPGA, address 0xe0000000 */
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#define CFG_SYS_CS1_BASE 0xe0000000
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#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
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#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
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#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
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#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
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#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
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#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
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#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
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#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
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#endif /* M5249 */
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