mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
169 lines
5.6 KiB
C
169 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h]
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*
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* (C) 2006 Andrew Victor
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* (C) Copyright 2010
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* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
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*
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* Definitions for the SoCs:
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* AT91SAM9260, AT91SAM9G20, AT91SAM9XE
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*
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* Note that those SoCs are mostly software and pin compatible,
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* therefore this file applies to all of them. Differences between
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* those SoCs are concentrated at the end of this file.
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*/
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#ifndef AT91SAM9260_H
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#define AT91SAM9260_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define ATMEL_ID_SYS 1 /* System Peripherals */
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#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
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#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
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#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */
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#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */
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#define ATMEL_ID_USART0 6 /* USART 0 */
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#define ATMEL_ID_USART1 7 /* USART 1 */
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#define ATMEL_ID_USART2 8 /* USART 2 */
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#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */
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#define ATMEL_ID_UDP 10 /* USB Device Port */
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#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */
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#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */
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#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */
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#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
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/* Reserved: 15 */
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/* Reserved: 16 */
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#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
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#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
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#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
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#define ATMEL_ID_UHP 20 /* USB Host port */
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#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */
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#define ATMEL_ID_ISI 22 /* Image Sensor Interface */
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#define ATMEL_ID_USART3 23 /* USART 3 */
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#define ATMEL_ID_USART4 24 /* USART 4 */
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/* USART5 or TWI1: 25 */
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#define ATMEL_ID_TC3 26 /* Timer Counter 3 */
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#define ATMEL_ID_TC4 27 /* Timer Counter 4 */
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#define ATMEL_ID_TC5 28 /* Timer Counter 5 */
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#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
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#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
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#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
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/*
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* User Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_TCB0 0xfffa0000
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#define ATMEL_BASE_TC0 0xfffa0000
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#define ATMEL_BASE_TC1 0xfffa0040
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#define ATMEL_BASE_TC2 0xfffa0080
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#define ATMEL_BASE_UDP0 0xfffa4000
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#define ATMEL_BASE_MCI 0xfffa8000
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#define ATMEL_BASE_TWI0 0xfffac000
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#define ATMEL_BASE_USART0 0xfffb0000
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#define ATMEL_BASE_USART1 0xfffb4000
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#define ATMEL_BASE_USART2 0xfffb8000
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#define ATMEL_BASE_SSC0 0xfffbc000
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#define ATMEL_BASE_ISI0 0xfffc0000
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#define ATMEL_BASE_EMAC0 0xfffc4000
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#define ATMEL_BASE_SPI0 0xfffc8000
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#define ATMEL_BASE_SPI1 0xfffcc000
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#define ATMEL_BASE_USART3 0xfffd0000
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#define ATMEL_BASE_USART4 0xfffd4000
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/* USART5 or TWI1: 0xfffd8000 */
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#define ATMEL_BASE_TCB1 0xfffdc000
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#define ATMEL_BASE_TC3 0xfffdc000
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#define ATMEL_BASE_TC4 0xfffdc040
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#define ATMEL_BASE_TC5 0xfffdc080
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#define ATMEL_BASE_ADC 0xfffe0000
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/* Reserved: 0xfffe4000 - 0xffffe7ff */
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/*
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* System Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_SYS 0xffffe800
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#define ATMEL_BASE_SDRAMC 0xffffea00
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#define ATMEL_BASE_SMC 0xffffec00
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#define ATMEL_BASE_MATRIX 0xffffee00
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#define ATMEL_BASE_CCFG 0xffffef14
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#define ATMEL_BASE_AIC 0xfffff000
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#define ATMEL_BASE_DBGU 0xfffff200
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#define ATMEL_BASE_PIOA 0xfffff400
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#define ATMEL_BASE_PIOB 0xfffff600
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#define ATMEL_BASE_PIOC 0xfffff800
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/* EEFC: 0xfffffa00 */
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#define ATMEL_BASE_PMC 0xfffffc00
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#define ATMEL_BASE_RSTC 0xfffffd00
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#define ATMEL_BASE_SHDWN 0xfffffd10
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#define ATMEL_BASE_RTT 0xfffffd20
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#define ATMEL_BASE_PIT 0xfffffd30
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#define ATMEL_BASE_WDT 0xfffffd40
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/* GPBR(non-XE SoCs): 0xfffffd50 */
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/* GPBR(XE SoCs): 0xfffffd60 */
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/* Reserved: 0xfffffd70 - 0xffffffff */
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/*
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* Internal Memory common on all these SoCs
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*/
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#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */
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#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
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/* SRAM or FLASH: 0x00200000 */
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/* SRAM: 0x00300000 */
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/* Reserved: 0x00400000 */
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#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */
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/*
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* External memory
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*/
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#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
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#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
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#define ATMEL_BASE_CS2 0x30000000
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#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
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#define ATMEL_BASE_CS4 0x50000000
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#define ATMEL_BASE_CS5 0x60000000
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#define ATMEL_BASE_CS6 0x70000000
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#define ATMEL_BASE_CS7 0x80000000
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
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/*
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* Other misc defines
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*/
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#ifndef CONFIG_DM_GPIO
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#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */
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#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
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#endif
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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/*
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* SoC specific defines
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*/
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#if defined(CONFIG_AT91SAM9XE)
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# define ATMEL_CPU_NAME "AT91SAM9XE"
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# define ATMEL_ID_TWI1 25 /* TWI 1 */
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# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */
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# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */
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# define ATMEL_BASE_TWI1 0xfffd8000
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# define ATMEL_BASE_EEFC 0xfffffa00
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# define ATMEL_BASE_GPBR 0xfffffd60
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#elif defined(CONFIG_AT91SAM9260)
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# define ATMEL_CPU_NAME "AT91SAM9260"
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# define ATMEL_ID_USART5 25 /* USART 5 */
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# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
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# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
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# define ATMEL_BASE_USART5 0xfffd8000
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# define ATMEL_BASE_GPBR 0xfffffd50
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#elif defined(CONFIG_AT91SAM9G20)
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# define ATMEL_CPU_NAME "AT91SAM9G20"
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# define ATMEL_ID_USART5 25 /* USART 5 */
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# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
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# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */
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# define ATMEL_BASE_USART5 0xfffd8000
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# define ATMEL_BASE_GPBR 0xfffffd50
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#endif
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#endif
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