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u-boot/arch/x86/cpu/ivybridge
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Simon Glass 72cd085aae x86: ivybridge: Add additional LPC init 
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
..
bd82x6x.c x86: ivybridge: Add additional LPC init 2014-11-25 06:34:01 -07:00
car.S x86: chromebook_link: Implement CAR support (cache as RAM) 2014-11-21 07:34:11 +01:00
cpu.c x86: ivybridge: Add LAPIC support 2014-11-21 07:34:15 +01:00
early_init.c x86: ivybridge: Add early init for PCH devices 2014-11-21 07:34:14 +01:00
early_me.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
Kconfig x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
lpc.c x86: ivybridge: Add additional LPC init 2014-11-25 06:34:01 -07:00
Makefile x86: ivybridge: Add PCH init 2014-11-25 06:34:00 -07:00
me_status.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
microcode_intel.c x86: ivybridge: Perform Intel microcode update on boot 2014-11-21 07:34:14 +01:00
pch.c x86: ivybridge: Add PCH init 2014-11-25 06:34:00 -07:00
pci.c x86: ivybridge: Add support for BD82x6x PCH 2014-11-25 06:34:00 -07:00
report_platform.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
sdram.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00