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https://github.com/AsahiLinux/u-boot
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206 lines
4.9 KiB
C
206 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 NXP
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*/
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#ifndef _ASM_ARCH_IMX8ULP_PCC_H
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#define _ASM_ARCH_IMX8ULP_PCC_H
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#include <asm/arch/cgc.h>
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enum pcc1_entry {
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ADC1_PCC1_SLOT = 34,
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};
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enum pcc3_entry {
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DMA1_MP_PCC3_SLOT = 1,
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DMA1_CH0_PCC3_SLOT = 2,
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DMA1_CH1_PCC3_SLOT = 3,
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DMA1_CH2_PCC3_SLOT = 4,
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DMA1_CH3_PCC3_SLOT = 5,
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DMA1_CH4_PCC3_SLOT = 6,
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DMA1_CH5_PCC3_SLOT = 7,
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DMA1_CH6_PCC3_SLOT = 8,
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DMA1_CH7_PCC3_SLOT = 9,
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DMA1_CH8_PCC3_SLOT = 10,
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DMA1_CH9_PCC3_SLOT = 11,
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DMA1_CH10_PCC3_SLOT = 12,
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DMA1_CH11_PCC3_SLOT = 13,
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DMA1_CH12_PCC3_SLOT = 14,
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DMA1_CH13_PCC3_SLOT = 15,
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DMA1_CH14_PCC3_SLOT = 16,
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DMA1_CH15_PCC3_SLOT = 17,
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DMA1_CH16_PCC3_SLOT = 18,
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DMA1_CH17_PCC3_SLOT = 19,
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DMA1_CH18_PCC3_SLOT = 20,
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DMA1_CH19_PCC3_SLOT = 21,
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DMA1_CH20_PCC3_SLOT = 22,
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DMA1_CH21_PCC3_SLOT = 23,
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DMA1_CH22_PCC3_SLOT = 24,
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DMA1_CH23_PCC3_SLOT = 25,
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DMA1_CH24_PCC3_SLOT = 26,
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DMA1_CH25_PCC3_SLOT = 27,
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DMA1_CH26_PCC3_SLOT = 28,
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DMA1_CH27_PCC3_SLOT = 29,
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DMA1_CH28_PCC3_SLOT = 30,
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DMA1_CH29_PCC3_SLOT = 31,
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DMA1_CH30_PCC3_SLOT = 32,
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DMA1_CH31_PCC3_SLOT = 33,
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MU0_B_PCC3_SLOT = 34,
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MU3_A_PCC3_SLOT = 35,
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LLWU1_PCC3_SLOT = 38,
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UPOWER_PCC3_SLOT = 40,
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WDOG3_PCC3_SLOT = 42,
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WDOG4_PCC3_SLOT = 43,
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CAAM_PCC3_SLOT = 46,
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XRDC_MGR_PCC3_SLOT = 47,
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SEMA42_1_PCC3_SLOT = 48,
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ROMCP1_PCC3_SLOT = 49,
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LPIT1_PCC3_SLOT = 50,
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TPM4_PCC3_SLOT = 51,
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TPM5_PCC3_SLOT = 52,
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FLEXIO1_PCC3_SLOT = 53,
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I3C2_PCC3_SLOT = 54,
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LPI2C4_PCC3_SLOT = 55,
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LPI2C5_PCC3_SLOT = 56,
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LPUART4_PCC3_SLOT = 57,
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LPUART5_PCC3_SLOT = 58,
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LPSPI4_PCC3_SLOT = 59,
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LPSPI5_PCC3_SLOT = 60,
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};
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enum pcc4_entry {
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FLEXSPI2_PCC4_SLOT = 1,
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TPM6_PCC4_SLOT = 2,
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TPM7_PCC4_SLOT = 3,
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LPI2C6_PCC4_SLOT = 4,
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LPI2C7_PCC4_SLOT = 5,
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LPUART6_PCC4_SLOT = 6,
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LPUART7_PCC4_SLOT = 7,
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SAI4_PCC4_SLOT = 8,
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SAI5_PCC4_SLOT = 9,
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PCTLE_PCC4_SLOT = 10,
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PCTLF_PCC4_SLOT = 11,
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SDHC0_PCC4_SLOT = 13,
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SDHC1_PCC4_SLOT = 14,
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SDHC2_PCC4_SLOT = 15,
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USB0_PCC4_SLOT = 16,
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USBPHY_PCC4_SLOT = 17,
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USB1_PCC4_SLOT = 18,
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USB1PHY_PCC4_SLOT = 19,
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USB_XBAR_PCC4_SLOT = 20,
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ENET_PCC4_SLOT = 21,
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SFA1_PCC4_SLOT = 22,
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RGPIOE_PCC4_SLOT = 30,
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RGPIOF_PCC4_SLOT = 31,
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};
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enum pcc5_entry {
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DMA2_MP_PCC5_SLOT = 0,
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DMA2_CH0_PCC5_SLOT = 1,
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DMA2_CH1_PCC5_SLOT = 2,
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DMA2_CH2_PCC5_SLOT = 3,
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DMA2_CH3_PCC5_SLOT = 4,
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DMA2_CH4_PCC5_SLOT = 5,
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DMA2_CH5_PCC5_SLOT = 6,
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DMA2_CH6_PCC5_SLOT = 7,
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DMA2_CH7_PCC5_SLOT = 8,
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DMA2_CH8_PCC5_SLOT = 9,
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DMA2_CH9_PCC5_SLOT = 10,
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DMA2_CH10_PCC5_SLOT = 11,
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DMA2_CH11_PCC5_SLOT = 12,
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DMA2_CH12_PCC5_SLOT = 13,
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DMA2_CH13_PCC5_SLOT = 14,
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DMA2_CH14_PCC5_SLOT = 15,
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DMA2_CH15_PCC5_SLOT = 16,
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DMA2_CH16_PCC5_SLOT = 17,
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DMA2_CH17_PCC5_SLOT = 18,
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DMA2_CH18_PCC5_SLOT = 19,
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DMA2_CH19_PCC5_SLOT = 20,
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DMA2_CH20_PCC5_SLOT = 21,
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DMA2_CH21_PCC5_SLOT = 22,
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DMA2_CH22_PCC5_SLOT = 23,
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DMA2_CH23_PCC5_SLOT = 24,
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DMA2_CH24_PCC5_SLOT = 25,
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DMA2_CH25_PCC5_SLOT = 26,
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DMA2_CH26_PCC5_SLOT = 27,
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DMA2_CH27_PCC5_SLOT = 28,
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DMA2_CH28_PCC5_SLOT = 29,
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DMA2_CH29_PCC5_SLOT = 30,
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DMA2_CH30_PCC5_SLOT = 31,
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DMA2_CH31_PCC5_SLOT = 32,
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MU2_B_PCC5_SLOT = 33,
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MU3_B_PCC5_SLOT = 34,
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SEMA42_2_PCC5_SLOT = 35,
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CMC2_PCC5_SLOT = 36,
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AVD_SIM_PCC5_SLOT = 37,
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LPAV_CGC_PCC5_SLOT = 38,
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PCC5_PCC5_SLOT = 39,
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TPM8_PCC5_SLOT = 40,
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SAI6_PCC5_SLOT = 41,
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SAI7_PCC5_SLOT = 42,
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SPDIF_PCC5_SLOT = 43,
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ISI_PCC5_SLOT = 44,
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CSI_REGS_PCC5_SLOT = 45,
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CSI_PCC5_SLOT = 47,
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DSI_PCC5_SLOT = 48,
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WDOG5_PCC5_SLOT = 50,
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EPDC_PCC5_SLOT = 51,
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PXP_PCC5_SLOT = 52,
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SFA2_PCC5_SLOT = 53,
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GPU2D_PCC5_SLOT = 60,
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GPU3D_PCC5_SLOT = 61,
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DCNANO_PCC5_SLOT = 62,
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LPDDR4_PCC5_SLOT = 66,
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CSI_CLK_UI_PCC5_SLOT = 67,
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CSI_CLK_ESC_PCC5_SLOT = 68,
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RGPIOD_PCC5_SLOT = 69,
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};
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/* PCC registers */
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#define PCC_PR_OFFSET 31
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#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
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#define PCC_CGC_OFFSET 30
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#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
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#define PCC_INUSE_OFFSET 29
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#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
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#define PCC_PCS_OFFSET 24
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#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
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#define PCC_FRAC_OFFSET 3
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#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
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#define PCC_PCD_OFFSET 0
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#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
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enum pcc_clksrc_type {
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CLKSRC_PER_PLAT = 0,
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CLKSRC_PER_BUS = 1,
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CLKSRC_NO_PCS = 2,
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};
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enum pcc_div_type {
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PCC_HAS_DIV,
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PCC_NO_DIV,
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};
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enum pcc_rst_b {
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PCC_HAS_RST_B,
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PCC_NO_RST_B,
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};
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/* This structure keeps info for each pcc slot */
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struct pcc_entry {
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u32 pcc_base;
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u32 pcc_slot;
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enum pcc_clksrc_type clksrc;
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enum pcc_div_type div;
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enum pcc_rst_b rst_b;
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};
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int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
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int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src);
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int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
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bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
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int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src);
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int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
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u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
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#endif
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