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https://github.com/AsahiLinux/u-boot
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afc13335a5
The Qualcomm device trees in U-Boot are currently not consistent with the upstream DTs used in the Linux kernel. While some bindings are similar to the official specification in the Linux kernel, several nodes have subtle differences, e.g. the "compatible"s or the exact specification of memory registers. This means that some of the Qualcomm-related U-Boot drivers are not compatible with the Linux DT (and vice versa). The SPMI node is one such example: the "core" region starts at 0x0200f000 in the upstream Linux MSM8916 DT, but in U-Boot it starts at 0x0200f800. The end result is normally the same, since the Linux SPMI driver simply adds the 0x800 internally. However, commitf5a2d6b4b0("spmi: msm: add arbiter version 5 support") imported this behavior into the U-Boot driver, without adjusting the DB410c/DB820c device trees. This means that the 0x800 offset is now added twice, breaking all SPMI read/write operations: Failed to find PMIC pon node. Check device tree Failed to find pm8916_gpios@c000 node. USB init failed: -6 starting USB... Bus ehci@78d9000: Failed to find pm8916_gpios@c000 node. probe failed, error -6 No working controllers found While the mistake is strictly speaking in the spmi-msm driver, fix the issue by making the SPMI nodes in the DB410c/DB820c consistent with the upstream Linux DT instead. Ideally we should even go a step further by fixing the remaining uses of custom bindings in the U-Boot drivers and moving to using the Linux DTs as-is. This would likely avoid such mistakes in the future and would also make the porting process much easier. Cc: Dzmitry Sankouski <dsankouski@gmail.com> Fixes:f5a2d6b4b0("spmi: msm: add arbiter version 5 support") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
142 lines
2.9 KiB
Text
142 lines
2.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm APQ8096 based Dragonboard 820C board device tree source
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*
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* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
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/ {
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model = "Qualcomm Technologies, Inc. DB820c";
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compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &blsp2_uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0 0x80000000 0 0xc0000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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smem_mem: smem_region@86300000 {
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reg = <0x0 0x86300000 0x0 0x200000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@300000 {
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compatible = "qcom,gcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x300000 0x90000>;
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};
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pinctrl: qcom,tlmm@1010000 {
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compatible = "qcom,tlmm-apq8096";
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reg = <0x1010000 0x400000>;
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blsp8_uart: uart {
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function = "blsp_uart8";
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pins = "GPIO_4", "GPIO_5";
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drive-strength = <DRIVE_STRENGTH_8MA>;
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bias-disable;
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};
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};
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blsp2_uart2: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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clock = <&gcc 4>;
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pinctrl-names = "uart";
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pinctrl-0 = <&blsp8_uart>;
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};
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sdhc2: sdhci@74a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
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index = <0x0>;
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bus-width = <4>;
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clock = <&gcc 0>;
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clock-frequency = <200000000>;
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};
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spmi_bus: spmi@400f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0400f000 0x1000>,
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<0x04400000 0x800000>,
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<0x04c00000 0x800000>,
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<0x05800000 0x200000>,
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<0x0400a000 0x002100>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pmic0: pm8994@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0x0 0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pm8994_pon: pm8994_pon@800 {
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compatible = "qcom,pm8994-pwrkey";
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reg = <0x800 0x96>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name="pm8994_key.";
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};
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pm8994_gpios: pm8994_gpios@c000 {
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compatible = "qcom,pm8994-gpio";
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reg = <0xc000 0x400>;
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gpio-controller;
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gpio-count = <24>;
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#gpio-cells = <2>;
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gpio-bank-name="pm8994.";
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};
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};
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pmic1: pm8994@1 {
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compatible = "qcom,spmi-pmic";
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reg = <0x1 0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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};
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};
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};
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#include "dragonboard820c-uboot.dtsi"
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