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https://github.com/AsahiLinux/u-boot
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055125171a
As Ocelot, Luton and Jaguar2, this family of SoCs are found in Microsemi Switches solution. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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void _machine_restart(void)
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{
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#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
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register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
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/* Set owner */
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reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
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reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
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/* Set boot mode */
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reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
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writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
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/* Read back in order to make BOOT mode setting active */
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reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
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/* Reset CPU only - still executing _here_. but from cache */
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writel(readl(BASE_CFG + ICPU_RESET) |
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ICPU_RESET_CORE_RST_CPU_ONLY |
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ICPU_RESET_CORE_RST_FORCE,
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BASE_CFG + ICPU_RESET);
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#else
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register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
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(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
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/* Make sure VCore is NOT protected from reset */
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clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
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/* Change to SPI bitbang for SPI reset workaround... */
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writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
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ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
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/* Do the global reset */
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writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
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#endif
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while (1)
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; /* NOP */
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}
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