mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
643eb6ea07
The TI J721E EVM system on module (SOM), the common processor board, and
the associated daughtercards have on-board I2C-based EEPROMs containing
board config data. Use the board detection infrastructure to do the
following:
1) Parse the J721E SOM EEPROM and populate items like board name, board
HW and SW revision as well as board serial number into the TI common
EEPROM data structure residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing associated I2C
addresses used for on-board EEPROMs containing daughter card-specific
data. If such a card is found, parse the EEPROM data such as for
additional Ethernet MAC addresses and populate those into U-Boot
accordingly
3) Dynamically apply daughter card DTB overlays to the U-Boot (proper)
DTB during SPL execution
4) Dynamically create an U-Boot ENV variable called name_overlays
during U-Boot execution containing a list of daugherboard-specific
DTB overlays based on daughercards found to be used during Kernel
boot.
This patch adds support for the J721E system on module boards containing
the actual SoC ("J721EX-PM2-SOM", accessed via CONFIG_EEPROM_CHIP_ADDRESS),
the common processor board ("J7X-BASE-CPB"), the Quad-Port Ethernet
Expansion Board ("J7X-VSC8514-ETH"), the infotainment board
("J7X-INFOTAN-EXP") as well as for the gateway/Ethernet switch/industrial
expansion board ("J7X-GESI-EXP").
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* K3: J721E SoC definitions, structures etc.
|
|
*
|
|
* (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
|
|
*/
|
|
#ifndef __ASM_ARCH_J721E_HARDWARE_H
|
|
#define __ASM_ARCH_J721E_HARDWARE_H
|
|
|
|
#include <config.h>
|
|
|
|
#define CTRL_MMR0_BASE 0x00100000
|
|
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
|
|
|
|
#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
|
|
#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
|
|
#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
|
|
#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
|
|
#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
|
|
#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
|
|
|
|
#define WKUP_CTRL_MMR0_BASE 0x43000000
|
|
#define MCU_CTRL_MMR0_BASE 0x40f00000
|
|
|
|
#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
|
|
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
|
|
#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
|
|
#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
|
|
#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
|
|
|
|
/*
|
|
* The CTRL_MMR0 memory space is divided into several equally-spaced
|
|
* partitions, so defining the partition size allows us to determine
|
|
* register addresses common to those partitions.
|
|
*/
|
|
#define CTRL_MMR0_PARTITION_SIZE 0x4000
|
|
|
|
/*
|
|
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
|
|
* shared register definitions.
|
|
*/
|
|
#define CTRLMMR_LOCK_KICK0 0x01008
|
|
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
|
|
#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
|
|
#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
|
|
#define CTRLMMR_LOCK_KICK1 0x0100c
|
|
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
|
|
|
/* MCU SCRATCHPAD usage */
|
|
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
|
|
|
|
#endif /* __ASM_ARCH_J721E_HARDWARE_H */
|