mirror of
https://github.com/AsahiLinux/u-boot
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6e73bb7e40
- In DM Ethernet, the old "egiga0" name is no longer valid, so replace it with Ethernet PHY name from device tree. Also, Ethernet PHY address is available so read it from device tree. Signed-off-by: Tony Dinh <mibodhi@gmail.com>
166 lines
3.4 KiB
C
166 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/mach-types.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include "sheevaplug.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
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SHEEVAPLUG_OE_VAL_HIGH,
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SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_UART0_RTS,
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MPP9_UART0_CTS,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_TSMP9,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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static int fdt_get_phy_addr(const char *path)
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{
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const void *fdt = gd->fdt_blob;
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const u32 *reg;
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const u32 *val;
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int node, phandle, addr;
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/* Find the node by its full path */
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node = fdt_path_offset(fdt, path);
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if (node >= 0) {
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/* Look up phy-handle */
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val = fdt_getprop(fdt, node, "phy-handle", NULL);
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if (val) {
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phandle = fdt32_to_cpu(*val);
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if (!phandle)
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return -1;
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/* Follow it to its node */
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node = fdt_node_offset_by_phandle(fdt, phandle);
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if (node) {
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/* Look up reg */
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reg = fdt_getprop(fdt, node, "reg", NULL);
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if (reg) {
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addr = fdt32_to_cpu(*reg);
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return addr;
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}
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}
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}
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}
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return -1;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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int phyaddr;
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char *name = "ethernet-controller@72000";
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char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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if (miiphy_set_current_dev(name))
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return;
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phyaddr = fdt_get_phy_addr(eth0_path);
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if (phyaddr < 0)
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, phyaddr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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