mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
cc89369fb0
Add sdram driver in U-Boot for get the correct sdram size from sys_reg, so that U-Boot can co-work with Rockchip loader or SPL to get different dram capability and then tell the kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
442 lines
9.8 KiB
C
442 lines
9.8 KiB
C
/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3368_H
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#define _ASM_ARCH_GRF_RK3368_H
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#include <common.h>
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struct rk3368_grf {
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u32 gpio1a_iomux;
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u32 gpio1b_iomux;
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u32 gpio1c_iomux;
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u32 gpio1d_iomux;
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u32 gpio2a_iomux;
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u32 gpio2b_iomux;
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u32 gpio2c_iomux;
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u32 gpio2d_iomux;
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u32 gpio3a_iomux;
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u32 gpio3b_iomux;
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u32 gpio3c_iomux;
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u32 gpio3d_iomux;
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u32 reserved[0x34];
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u32 gpio1a_pull;
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u32 gpio1b_pull;
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u32 gpio1c_pull;
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u32 gpio1d_pull;
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u32 gpio2a_pull;
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u32 gpio2b_pull;
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u32 gpio2c_pull;
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u32 gpio2d_pull;
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u32 gpio3a_pull;
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u32 gpio3b_pull;
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u32 gpio3c_pull;
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u32 gpio3d_pull;
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u32 reserved1[0x34];
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u32 gpio1a_drv;
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u32 gpio1b_drv;
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u32 gpio1c_drv;
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u32 gpio1d_drv;
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u32 gpio2a_drv;
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u32 gpio2b_drv;
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u32 gpio2c_drv;
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u32 gpio2d_drv;
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u32 gpio3a_drv;
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u32 gpio3b_drv;
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u32 gpio3c_drv;
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u32 gpio3d_drv;
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u32 reserved2[0x34];
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u32 gpio1l_sr;
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u32 gpio1h_sr;
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u32 gpio2l_sr;
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u32 gpio2h_sr;
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u32 gpio3l_sr;
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u32 gpio3h_sr;
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u32 reserved3[0x1a];
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u32 gpio_smt;
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u32 reserved4[0x1f];
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u32 soc_con0;
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u32 soc_con1;
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u32 soc_con2;
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u32 soc_con3;
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u32 soc_con4;
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u32 soc_con5;
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u32 soc_con6;
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u32 soc_con7;
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u32 soc_con8;
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u32 soc_con9;
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u32 soc_con10;
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u32 soc_con11;
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u32 soc_con12;
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u32 soc_con13;
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u32 soc_con14;
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u32 soc_con15;
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u32 soc_con16;
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u32 soc_con17;
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};
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check_member(rk3368_grf, soc_con17, 0x444);
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struct rk3368_pmu_grf {
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u32 gpio0a_iomux;
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u32 gpio0b_iomux;
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u32 gpio0c_iomux;
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u32 gpio0d_iomux;
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u32 gpio0a_pull;
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u32 gpio0b_pull;
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u32 gpio0c_pull;
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u32 gpio0d_pull;
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u32 gpio0a_drv;
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u32 gpio0b_drv;
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u32 gpio0c_drv;
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u32 gpio0d_drv;
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u32 gpio0l_sr;
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u32 gpio0h_sr;
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u32 reserved[(0x200 - 0x34) / 4 - 1];
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u32 os_reg[4];
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};
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check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
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/*GRF_GPIO0C_IOMUX*/
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enum {
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GPIO0C7_SHIFT = 14,
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GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
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GPIO0C7_GPIO = 0,
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GPIO0C7_LCDC_D19,
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GPIO0C7_TRACE_D9,
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GPIO0C7_UART1_RTSN,
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GPIO0C6_SHIFT = 12,
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GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
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GPIO0C6_GPIO = 0,
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GPIO0C6_LCDC_D18,
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GPIO0C6_TRACE_D8,
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GPIO0C6_UART1_CTSN,
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GPIO0C5_SHIFT = 10,
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GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
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GPIO0C5_GPIO = 0,
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GPIO0C5_LCDC_D17,
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GPIO0C5_TRACE_D7,
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GPIO0C5_UART1_SOUT,
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GPIO0C4_SHIFT = 8,
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GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
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GPIO0C4_GPIO = 0,
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GPIO0C4_LCDC_D16,
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GPIO0C4_TRACE_D6,
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GPIO0C4_UART1_SIN,
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GPIO0C3_SHIFT = 6,
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GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
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GPIO0C3_GPIO = 0,
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GPIO0C3_LCDC_D15,
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GPIO0C3_TRACE_D5,
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GPIO0C3_MCU_JTAG_TDO,
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GPIO0C2_SHIFT = 4,
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GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
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GPIO0C2_GPIO = 0,
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GPIO0C2_LCDC_D14,
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GPIO0C2_TRACE_D4,
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GPIO0C2_MCU_JTAG_TDI,
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GPIO0C1_SHIFT = 2,
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GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
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GPIO0C1_GPIO = 0,
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GPIO0C1_LCDC_D13,
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GPIO0C1_TRACE_D3,
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GPIO0C1_MCU_JTAG_TRTSN,
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GPIO0C0_SHIFT = 0,
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GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
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GPIO0C0_GPIO = 0,
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GPIO0C0_LCDC_D12,
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GPIO0C0_TRACE_D2,
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GPIO0C0_MCU_JTAG_TDO,
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};
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/*GRF_GPIO0D_IOMUX*/
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enum {
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GPIO0D7_SHIFT = 14,
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GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
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GPIO0D7_GPIO = 0,
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GPIO0D7_LCDC_DCLK,
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GPIO0D7_TRACE_CTL,
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GPIO0D7_PMU_DEBUG5,
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GPIO0D6_SHIFT = 12,
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GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
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GPIO0D6_GPIO = 0,
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GPIO0D6_LCDC_DEN,
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GPIO0D6_TRACE_CLK,
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GPIO0D6_PMU_DEBUG4,
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GPIO0D5_SHIFT = 10,
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GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
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GPIO0D5_GPIO = 0,
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GPIO0D5_LCDC_VSYNC,
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GPIO0D5_TRACE_D15,
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GPIO0D5_PMU_DEBUG3,
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GPIO0D4_SHIFT = 8,
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GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
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GPIO0D4_GPIO = 0,
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GPIO0D4_LCDC_HSYNC,
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GPIO0D4_TRACE_D14,
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GPIO0D4_PMU_DEBUG2,
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GPIO0D3_SHIFT = 6,
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GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
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GPIO0D3_GPIO = 0,
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GPIO0D3_LCDC_D23,
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GPIO0D3_TRACE_D13,
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GPIO0D3_UART4_SIN,
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GPIO0D2_SHIFT = 4,
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GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
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GPIO0D2_GPIO = 0,
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GPIO0D2_LCDC_D22,
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GPIO0D2_TRACE_D12,
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GPIO0D2_UART4_SOUT,
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GPIO0D1_SHIFT = 2,
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GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
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GPIO0D1_GPIO = 0,
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GPIO0D1_LCDC_D21,
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GPIO0D1_TRACE_D11,
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GPIO0D1_UART4_RTSN,
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GPIO0D0_SHIFT = 0,
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GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
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GPIO0D0_GPIO = 0,
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GPIO0D0_LCDC_D20,
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GPIO0D0_TRACE_D10,
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GPIO0D0_UART4_CTSN,
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};
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/*GRF_GPIO2A_IOMUX*/
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enum {
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GPIO2A7_SHIFT = 14,
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GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
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GPIO2A7_GPIO = 0,
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GPIO2A7_SDMMC0_D2,
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GPIO2A7_JTAG_TCK,
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GPIO2A6_SHIFT = 12,
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GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
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GPIO2A6_GPIO = 0,
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GPIO2A6_SDMMC0_D1,
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GPIO2A6_UART2_SIN,
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GPIO2A5_SHIFT = 10,
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GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
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GPIO2A5_GPIO = 0,
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GPIO2A5_SDMMC0_D0,
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GPIO2A5_UART2_SOUT,
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GPIO2A4_SHIFT = 8,
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GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
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GPIO2A4_GPIO = 0,
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GPIO2A4_FLASH_DQS,
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GPIO2A4_EMMC_CLKO,
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GPIO2A3_SHIFT = 6,
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GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
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GPIO2A3_GPIO = 0,
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GPIO2A3_FLASH_CSN3,
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GPIO2A3_EMMC_RSTNO,
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GPIO2A2_SHIFT = 4,
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GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
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GPIO2A2_GPIO = 0,
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GPIO2A2_FLASH_CSN2,
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GPIO2A1_SHIFT = 2,
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GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
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GPIO2A1_GPIO = 0,
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GPIO2A1_FLASH_CSN1,
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GPIO2A0_SHIFT = 0,
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GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
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GPIO2A0_GPIO = 0,
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GPIO2A0_FLASH_CSN0,
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};
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/*GRF_GPIO2D_IOMUX*/
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enum {
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GPIO2D7_SHIFT = 14,
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GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
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GPIO2D7_GPIO = 0,
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GPIO2D7_SDIO0_D3,
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GPIO2D6_SHIFT = 12,
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GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
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GPIO2D6_GPIO = 0,
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GPIO2D6_SDIO0_D2,
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GPIO2D5_SHIFT = 10,
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GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
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GPIO2D5_GPIO = 0,
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GPIO2D5_SDIO0_D1,
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GPIO2D4_SHIFT = 8,
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GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
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GPIO2D4_GPIO = 0,
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GPIO2D4_SDIO0_D0,
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GPIO2D3_SHIFT = 6,
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GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
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GPIO2D3_GPIO = 0,
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GPIO2D3_UART0_RTS0,
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GPIO2D2_SHIFT = 4,
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GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
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GPIO2D2_GPIO = 0,
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GPIO2D2_UART0_CTS0,
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GPIO2D1_SHIFT = 2,
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GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART0_SOUT,
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GPIO2D0_SHIFT = 0,
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GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
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GPIO2D0_GPIO = 0,
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GPIO2D0_UART0_SIN,
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};
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/*GRF_GPIO3C_IOMUX*/
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enum {
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GPIO3C7_SHIFT = 14,
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GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
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GPIO3C7_GPIO = 0,
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GPIO3C7_EDPHDMI_CECINOUT,
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GPIO3C7_ISP_FLASHTRIGIN,
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GPIO3C6_SHIFT = 12,
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GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
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GPIO3C6_GPIO = 0,
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GPIO3C6_MAC_CLK,
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GPIO3C6_ISP_SHUTTERTRIG,
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GPIO3C5_SHIFT = 10,
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GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
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GPIO3C5_GPIO = 0,
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GPIO3C5_MAC_RXER,
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GPIO3C5_ISP_PRELIGHTTRIG,
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GPIO3C4_SHIFT = 8,
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GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
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GPIO3C4_GPIO = 0,
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GPIO3C4_MAC_RXDV,
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GPIO3C4_ISP_FLASHTRIGOUT,
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GPIO3C3_SHIFT = 6,
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GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
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GPIO3C3_GPIO = 0,
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GPIO3C3_MAC_RXDV,
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GPIO3C3_EMMC_RSTNO,
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GPIO3C2_SHIFT = 4,
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GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
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GPIO3C2_MAC_MDC = 0,
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GPIO3C2_ISP_SHUTTEREN,
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GPIO3C1_SHIFT = 2,
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GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
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GPIO3C1_GPIO = 0,
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GPIO3C1_MAC_RXD2,
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GPIO3C1_UART3_RTSN,
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GPIO3C0_SHIFT = 0,
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GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
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GPIO3C0_GPIO = 0,
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GPIO3C0_MAC_RXD1,
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GPIO3C0_UART3_CTSN,
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GPIO3C0_GPS_RFCLK,
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};
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/*GRF_GPIO3D_IOMUX*/
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enum {
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GPIO3D7_SHIFT = 14,
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GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
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GPIO3D7_GPIO = 0,
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GPIO3D7_SC_VCC18V,
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GPIO3D7_I2C2_SDA,
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GPIO3D7_GPUJTAG_TCK,
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GPIO3D6_SHIFT = 12,
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GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
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GPIO3D6_GPIO = 0,
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GPIO3D6_IR_TX,
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GPIO3D6_UART3_SOUT,
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GPIO3D6_PWM3,
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GPIO3D5_SHIFT = 10,
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GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
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GPIO3D5_GPIO = 0,
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GPIO3D5_IR_RX,
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GPIO3D5_UART3_SIN,
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GPIO3D4_SHIFT = 8,
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GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
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GPIO3D4_GPIO = 0,
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GPIO3D4_MAC_TXCLKOUT,
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GPIO3D4_SPI1_CSN1,
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GPIO3D3_SHIFT = 6,
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GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
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GPIO3D3_GPIO = 0,
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GPIO3D3_HDMII2C_SCL,
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GPIO3D3_I2C5_SCL,
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GPIO3D2_SHIFT = 4,
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GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
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GPIO3D2_GPIO = 0,
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GPIO3D2_HDMII2C_SDA,
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GPIO3D2_I2C5_SDA,
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GPIO3D1_SHIFT = 2,
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GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
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GPIO3D1_GPIO = 0,
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GPIO3D1_MAC_RXCLKIN,
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GPIO3D1_I2C4_SCL,
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GPIO3D0_SHIFT = 0,
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GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
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GPIO3D0_GPIO = 0,
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GPIO3D0_MAC_MDIO,
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GPIO3D0_I2C4_SDA,
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};
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/*GRF_SOC_CON11/12/13*/
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enum {
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MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON12*/
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enum {
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MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON13*/
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enum {
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MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
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MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
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};
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/*GRF_SOC_CON14*/
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enum {
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MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
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MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
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MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
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MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
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MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
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MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
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MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
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MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
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};
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#endif
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