mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
a821c4af79
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
85 lines
2 KiB
C
85 lines
2 KiB
C
/*
|
|
* Copyright 2016 Google Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <pwm.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/pwm.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
struct tegra_pwm_priv {
|
|
struct pwm_ctlr *regs;
|
|
};
|
|
|
|
static int tegra_pwm_set_config(struct udevice *dev, uint channel,
|
|
uint period_ns, uint duty_ns)
|
|
{
|
|
struct tegra_pwm_priv *priv = dev_get_priv(dev);
|
|
struct pwm_ctlr *regs = priv->regs;
|
|
uint pulse_width;
|
|
u32 reg;
|
|
|
|
if (channel >= 4)
|
|
return -EINVAL;
|
|
debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
|
|
/* We ignore the period here and just use 32KHz */
|
|
clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
|
|
|
|
pulse_width = duty_ns * 255 / period_ns;
|
|
|
|
reg = pulse_width << PWM_WIDTH_SHIFT;
|
|
reg |= 1 << PWM_DIVIDER_SHIFT;
|
|
writel(reg, ®s[channel].control);
|
|
debug("%s: pulse_width=%u\n", __func__, pulse_width);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
|
|
{
|
|
struct tegra_pwm_priv *priv = dev_get_priv(dev);
|
|
struct pwm_ctlr *regs = priv->regs;
|
|
|
|
if (channel >= 4)
|
|
return -EINVAL;
|
|
debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
|
|
clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK,
|
|
enable ? PWM_ENABLE_MASK : 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct tegra_pwm_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->regs = (struct pwm_ctlr *)devfdt_get_addr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pwm_ops tegra_pwm_ops = {
|
|
.set_config = tegra_pwm_set_config,
|
|
.set_enable = tegra_pwm_set_enable,
|
|
};
|
|
|
|
static const struct udevice_id tegra_pwm_ids[] = {
|
|
{ .compatible = "nvidia,tegra124-pwm" },
|
|
{ .compatible = "nvidia,tegra20-pwm" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(tegra_pwm) = {
|
|
.name = "tegra_pwm",
|
|
.id = UCLASS_PWM,
|
|
.of_match = tegra_pwm_ids,
|
|
.ops = &tegra_pwm_ops,
|
|
.ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
|
|
};
|