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https://github.com/AsahiLinux/u-boot
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03c609f69b
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the code now deals with both PLL clocks and source clocks. This also tidied up the assert() to match the one sent upstream, and fixes an error in the PWM id. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Tegra2 Clock control functions */
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#include <asm/io.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tegra2.h>
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#include <common.h>
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/*
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* Get the oscillator frequency, from the corresponding hardware configuration
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* field.
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*/
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enum clock_osc_freq clock_get_osc_freq(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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reg = readl(&clkrst->crc_osc_ctrl);
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return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
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}
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unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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u32 divp, u32 cpcon, u32 lfcon)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 data;
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struct clk_pll *pll;
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assert(clock_id_isvalid(clkid));
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pll = &clkrst->crc_pll[clkid];
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/*
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* We cheat by treating all PLL (except PLLU) in the same fashion.
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* This works only because:
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* - same fields are always mapped at same offsets, except DCCON
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* - DCCON is always 0, doesn't conflict
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* - M,N, P of PLLP values are ignored for PLLP
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*/
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data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
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writel(data, &pll->pll_misc);
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data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
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(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
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if (clkid == CLOCK_ID_USB)
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data |= divp << PLLU_VCO_FREQ_SHIFT;
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else
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data |= divp << PLL_DIVP_SHIFT;
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writel(data, &pll->pll_base);
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/* calculate the stable time */
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return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
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}
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void clock_set_enable(enum periph_id periph_id, int enable)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
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u32 reg;
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/* Enable/disable the clock to this peripheral */
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assert(clock_periph_id_isvalid(periph_id));
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reg = readl(clk);
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if (enable)
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reg |= PERIPH_MASK(periph_id);
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else
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reg &= ~PERIPH_MASK(periph_id);
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writel(reg, clk);
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}
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void clock_enable(enum periph_id clkid)
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{
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clock_set_enable(clkid, 1);
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}
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void clock_disable(enum periph_id clkid)
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{
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clock_set_enable(clkid, 0);
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}
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void reset_set_enable(enum periph_id periph_id, int enable)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
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u32 reg;
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/* Enable/disable reset to the peripheral */
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assert(clock_periph_id_isvalid(periph_id));
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reg = readl(reset);
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if (enable)
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reg |= PERIPH_MASK(periph_id);
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else
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reg &= ~PERIPH_MASK(periph_id);
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writel(reg, reset);
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}
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void reset_periph(enum periph_id periph_id, int us_delay)
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{
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/* Put peripheral into reset */
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reset_set_enable(periph_id, 1);
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udelay(us_delay);
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/* Remove reset */
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reset_set_enable(periph_id, 0);
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udelay(us_delay);
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}
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void reset_cmplx_set_enable(int cpu, int which, int reset)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 mask;
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/* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
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assert(cpu >= 0 && cpu < 2);
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mask = which << cpu;
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/* either enable or disable those reset for that CPU */
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if (reset)
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writel(mask, &clkrst->crc_cpu_cmplx_set);
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else
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writel(mask, &clkrst->crc_cpu_cmplx_clr);
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}
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