mirror of
https://github.com/AsahiLinux/u-boot
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f98984cb19
define there own I/O functions.
(Needed for the pcs440ep board).
- The default I/O Functions are again 8 Bit accesses.
- Added CONFIG_CMD_IDE for the pcs440ep Board.
Signed-off-by: Heiko Schocher <hs@denx.de>
211 lines
6.7 KiB
C
211 lines
6.7 KiB
C
/* originally from linux source.
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* removed the dependencies on CONFIG_ values
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* removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
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* Modified By Rob Taylor, Flying Pig Systems, 2000
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*/
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#ifndef _PPC_IO_H
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#define _PPC_IO_H
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#include <linux/config.h>
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#include <asm/byteorder.h>
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#define SIO_CONFIG_RA 0x398
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#define SIO_CONFIG_RD 0x399
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#ifndef _IO_BASE
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#define _IO_BASE 0
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#endif
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#define readb(addr) in_8((volatile u8 *)(addr))
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#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
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#if !defined(__BIG_ENDIAN)
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#define readw(addr) (*(volatile u16 *) (addr))
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#define readl(addr) (*(volatile u32 *) (addr))
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#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
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#else
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#define readw(addr) in_le16((volatile u16 *)(addr))
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#define readl(addr) in_le32((volatile u32 *)(addr))
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#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
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#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
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#endif
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/*
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* The insw/outsw/insl/outsl macros don't do byte-swapping.
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* They are only used in practice for transferring buffers which
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* are arrays of bytes, and byte-swapping is not appropriate in
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* that case. - paulus
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*/
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#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define inb(port) in_8((u8 *)((port)+_IO_BASE))
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#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
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#if !defined(__BIG_ENDIAN)
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#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
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#else
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#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
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#endif
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#define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
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#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
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#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
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#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
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#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
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#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
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extern void _insb(volatile u8 *port, void *buf, int ns);
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extern void _outsb(volatile u8 *port, const void *buf, int ns);
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extern void _insw(volatile u16 *port, void *buf, int ns);
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extern void _outsw(volatile u16 *port, const void *buf, int ns);
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extern void _insl(volatile u32 *port, void *buf, int nl);
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extern void _outsl(volatile u32 *port, const void *buf, int nl);
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extern void _insw_ns(volatile u16 *port, void *buf, int ns);
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extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
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extern void _insl_ns(volatile u32 *port, void *buf, int nl);
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extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
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/*
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* The *_ns versions below don't do byte-swapping.
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* Neither do the standard versions now, these are just here
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* for older code.
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*/
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#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define IO_SPACE_LIMIT ~0
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/*
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* Enforce In-order Execution of I/O:
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* Acts as a barrier to ensure all previous I/O accesses have
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* completed before any further ones are issued.
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*/
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static inline void eieio(void)
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{
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__asm__ __volatile__ ("eieio" : : : "memory");
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}
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static inline void sync(void)
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{
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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static inline void isync(void)
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{
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__asm__ __volatile__ ("isync" : : : "memory");
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}
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/* Enforce in-order execution of data I/O.
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* No distinction between read/write on PPC; use eieio for all three.
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*/
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#define iobarrier_rw() eieio()
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#define iobarrier_r() eieio()
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#define iobarrier_w() eieio()
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/*
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* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
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*
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* Read operations have additional twi & isync to make sure the read
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* is actually performed (i.e. the data has come back) before we start
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* executing any following instructions.
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*/
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#define __iomem
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extern inline int in_8(const volatile unsigned char __iomem *addr)
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{
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int ret;
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__asm__ __volatile__(
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"sync; lbz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_8(volatile unsigned char __iomem *addr, int val)
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{
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline int in_le16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline int in_be16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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#endif
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