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https://github.com/AsahiLinux/u-boot
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38b0852b0e
Set up opcode extension and enable/disable DTR mode based on whether the command is DTR or not. xSPI flashes can have a 4-byte dummy address associated with some commands like the Read Status Register command in octal DTR mode. Since the flash does not support sending the dummy address, we can not use automatic write completion polling in DTR mode. Further, no write completion polling makes it impossible to use DAC mode for DTR writes. In that mode, the controller does not know beforehand how long a write will be and so it can de-assert Chip Select (CS#) at any time. Once CS# is de-assert, the flash will go into burning phase. But since the controller does not do write completion polling, it does not know when the flash is busy and might send in writes while the flash is not ready. So, disable write completion polling and make writes go through indirect mode for DTR writes and let spi-mem take care of polling the SR. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*/
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#ifndef __CADENCE_QSPI_H__
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#define __CADENCE_QSPI_H__
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#include <reset.h>
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#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
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#define CQSPI_NO_DECODER_MAX_CS 4
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#define CQSPI_DECODER_MAX_CS 16
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#define CQSPI_READ_CAPTURE_MAX_DELAY 16
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struct cadence_spi_plat {
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unsigned int ref_clk_hz;
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unsigned int max_hz;
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void *regbase;
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void *ahbbase;
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bool is_decoded_cs;
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u32 fifo_depth;
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u32 fifo_width;
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u32 trigger_address;
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fdt_addr_t ahbsize;
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bool use_dac_mode;
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int read_delay;
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u32 wr_delay;
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/* Flash parameters */
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u32 page_size;
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u32 block_size;
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u32 tshsl_ns;
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u32 tsd2d_ns;
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u32 tchsh_ns;
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u32 tslch_ns;
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/* Transaction protocol parameters. */
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u8 inst_width;
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u8 addr_width;
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u8 data_width;
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bool dtr;
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};
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struct cadence_spi_priv {
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void *regbase;
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void *ahbbase;
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size_t cmd_len;
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u8 cmd_buf[32];
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size_t data_len;
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int qspi_is_init;
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unsigned int qspi_calibrated_hz;
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unsigned int qspi_calibrated_cs;
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unsigned int previous_hz;
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struct reset_ctl_bulk resets;
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};
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/* Functions call declaration */
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void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat);
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void cadence_qspi_apb_controller_enable(void *reg_base_addr);
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void cadence_qspi_apb_controller_disable(void *reg_base_addr);
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void cadence_qspi_apb_dac_mode_enable(void *reg_base);
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int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
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const struct spi_mem_op *op);
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void cadence_qspi_apb_chipselect(void *reg_base,
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unsigned int chip_select, unsigned int decoder_enable);
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void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
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void cadence_qspi_apb_config_baudrate_div(void *reg_base,
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unsigned int ref_clk_hz, unsigned int sclk_hz);
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void cadence_qspi_apb_delay(void *reg_base,
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unsigned int ref_clk, unsigned int sclk_hz,
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unsigned int tshsl_ns, unsigned int tsd2d_ns,
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unsigned int tchsh_ns, unsigned int tslch_ns);
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void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
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void cadence_qspi_apb_readdata_capture(void *reg_base,
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unsigned int bypass, unsigned int delay);
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#endif /* __CADENCE_QSPI_H__ */
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