mirror of
https://github.com/AsahiLinux/u-boot
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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
366 lines
8.6 KiB
C
366 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <zynqmp_firmware.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#define LOCK 0
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#define SPLIT 1
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#define HALT 0
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#define RELEASE 1
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#define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF
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#define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000
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#define ZYNQMP_R5_LOVEC_ADDR 0x0
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#define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01
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#define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04
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#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
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#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
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#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
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#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
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#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01
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#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02
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#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
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#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000
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#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000
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#define ZYNQMP_TCM_BOTH_SIZE 0x40000
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#define ZYNQMP_CORE_APU0 0
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#define ZYNQMP_CORE_APU3 3
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#define ZYNQMP_CORE_RPU0 4
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#define ZYNQMP_CORE_RPU1 5
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#define ZYNQMP_MAX_CORES 6
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#define ZYNQMP_RPU0_USE_MASK BIT(1)
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#define ZYNQMP_RPU1_USE_MASK BIT(2)
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int is_core_valid(unsigned int core)
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{
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if (core < ZYNQMP_MAX_CORES)
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return 1;
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return 0;
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}
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int cpu_reset(u32 nr)
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{
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puts("Feature is not implemented.\n");
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return 0;
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}
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static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
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{
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u32 tmp;
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if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
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tmp = readl(&rpu_base->rpu0_cfg);
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if (halt == HALT)
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tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
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else
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tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
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writel(tmp, &rpu_base->rpu0_cfg);
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}
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if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
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tmp = readl(&rpu_base->rpu1_cfg);
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if (halt == HALT)
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tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
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else
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tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
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writel(tmp, &rpu_base->rpu1_cfg);
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}
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}
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static void set_r5_tcm_mode(u8 mode)
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{
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u32 tmp;
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tmp = readl(&rpu_base->rpu_glbl_ctrl);
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if (mode == LOCK) {
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tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
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tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
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ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
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} else {
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tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
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tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
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ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
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}
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writel(tmp, &rpu_base->rpu_glbl_ctrl);
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}
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static void set_r5_reset(u32 nr, u8 mode)
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{
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u32 tmp;
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tmp = readl(&crlapb_base->rst_lpd_top);
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if (mode == LOCK) {
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tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
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ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
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ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
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} else {
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if (nr == ZYNQMP_CORE_RPU0) {
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tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK;
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if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK)
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tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
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} else {
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tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
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if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK)
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tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
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}
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}
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writel(tmp, &crlapb_base->rst_lpd_top);
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}
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static void release_r5_reset(u32 nr, u8 mode)
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{
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u32 tmp;
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tmp = readl(&crlapb_base->rst_lpd_top);
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if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
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tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
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ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
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if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
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tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
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ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
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writel(tmp, &crlapb_base->rst_lpd_top);
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}
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static void enable_clock_r5(void)
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{
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u32 tmp;
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tmp = readl(&crlapb_base->cpu_r5_ctrl);
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tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
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writel(tmp, &crlapb_base->cpu_r5_ctrl);
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/* Give some delay for clock
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* to propagate */
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udelay(0x500);
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}
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static int check_r5_mode(void)
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{
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u32 tmp;
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tmp = readl(&rpu_base->rpu_glbl_ctrl);
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if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
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return SPLIT;
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return LOCK;
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}
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int cpu_disable(u32 nr)
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{
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if (nr <= ZYNQMP_CORE_APU3) {
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u32 val = readl(&crfapb_base->rst_fpd_apu);
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val |= 1 << nr;
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writel(val, &crfapb_base->rst_fpd_apu);
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} else {
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set_r5_reset(nr, check_r5_mode());
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}
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return 0;
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}
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int cpu_status(u32 nr)
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{
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if (nr <= ZYNQMP_CORE_APU3) {
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u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
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u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
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nr * 8);
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u32 val = readl(&crfapb_base->rst_fpd_apu);
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val &= 1 << nr;
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printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
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nr, val ? "OFF" : "ON" , addr_high, addr_low);
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} else {
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u32 val = readl(&crlapb_base->rst_lpd_top);
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val &= 1 << (nr - 4);
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printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
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}
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return 0;
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}
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static void set_r5_start(u8 high)
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{
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u32 tmp;
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tmp = readl(&rpu_base->rpu0_cfg);
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if (high)
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tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
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else
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tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
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writel(tmp, &rpu_base->rpu0_cfg);
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tmp = readl(&rpu_base->rpu1_cfg);
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if (high)
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tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
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else
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tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
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writel(tmp, &rpu_base->rpu1_cfg);
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}
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static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr)
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{
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if (boot_addr) {
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u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR;
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if (nr == ZYNQMP_CORE_RPU1)
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tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR;
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/*
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* Boot trampoline is simple ASM code below.
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*
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* b over;
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* label:
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* .word 0
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* over: ldr r0, =label
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* ldr r1, [r0]
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* bx r1
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*/
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debug("Write boot trampoline for %x\n", boot_addr);
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writel(0xea000000, tcm_start_addr);
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writel(boot_addr, tcm_start_addr + 0x4);
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writel(0xe59f0004, tcm_start_addr + 0x8);
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writel(0xe5901000, tcm_start_addr + 0xc);
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writel(0xe12fff11, tcm_start_addr + 0x10);
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writel(0x00000004, tcm_start_addr + 0x14);
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}
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}
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void initialize_tcm(bool mode)
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{
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if (!mode) {
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set_r5_tcm_mode(LOCK);
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set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
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enable_clock_r5();
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release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
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} else {
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set_r5_tcm_mode(SPLIT);
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set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
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set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
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enable_clock_r5();
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release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
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release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
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}
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}
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static void mark_r5_used(u32 nr, u8 mode)
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{
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u32 mask = 0;
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if (mode == LOCK) {
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mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
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} else {
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switch (nr) {
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case ZYNQMP_CORE_RPU0:
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mask = ZYNQMP_RPU0_USE_MASK;
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break;
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case ZYNQMP_CORE_RPU1:
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mask = ZYNQMP_RPU1_USE_MASK;
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break;
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default:
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return;
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}
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}
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zynqmp_mmio_write((ulong)&pmu_base->gen_storage4, mask, mask);
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}
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int cpu_release(u32 nr, int argc, char *const argv[])
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{
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if (nr <= ZYNQMP_CORE_APU3) {
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u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
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/* HIGH */
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writel((u32)(boot_addr >> 32),
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((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
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/* LOW */
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writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
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((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
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u32 val = readl(&crfapb_base->rst_fpd_apu);
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val &= ~(1 << nr);
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writel(val, &crfapb_base->rst_fpd_apu);
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} else {
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if (argc != 2) {
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printf("Invalid number of arguments to release.\n");
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printf("<addr> <mode>-Start addr lockstep or split\n");
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return 1;
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}
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u32 boot_addr = hextoul(argv[0], NULL);
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u32 boot_addr_uniq = 0;
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if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
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boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
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printf("Using TCM jump trampoline for address 0x%x\n",
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boot_addr);
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/* Save boot address for later usage */
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boot_addr_uniq = boot_addr;
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/*
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* R5 needs to start from LOVEC at TCM
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* OCM will be probably occupied by ATF
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*/
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boot_addr = ZYNQMP_R5_LOVEC_ADDR;
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}
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/*
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* Since we don't know where the user may have loaded the image
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* for an R5 we have to flush all the data cache to ensure
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* the R5 sees it.
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*/
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flush_dcache_all();
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if (!strncmp(argv[1], "lockstep", 8)) {
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if (nr != ZYNQMP_CORE_RPU0) {
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printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
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return 1;
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}
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printf("R5 lockstep mode\n");
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set_r5_reset(nr, LOCK);
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set_r5_tcm_mode(LOCK);
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set_r5_halt_mode(nr, HALT, LOCK);
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set_r5_start(boot_addr);
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enable_clock_r5();
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release_r5_reset(nr, LOCK);
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dcache_disable();
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write_tcm_boot_trampoline(nr, boot_addr_uniq);
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dcache_enable();
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set_r5_halt_mode(nr, RELEASE, LOCK);
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mark_r5_used(nr, LOCK);
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} else if (!strncmp(argv[1], "split", 5)) {
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printf("R5 split mode\n");
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set_r5_reset(nr, SPLIT);
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set_r5_tcm_mode(SPLIT);
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set_r5_halt_mode(nr, HALT, SPLIT);
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set_r5_start(boot_addr);
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enable_clock_r5();
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release_r5_reset(nr, SPLIT);
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dcache_disable();
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write_tcm_boot_trampoline(nr, boot_addr_uniq);
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dcache_enable();
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set_r5_halt_mode(nr, RELEASE, SPLIT);
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mark_r5_used(nr, SPLIT);
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} else {
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printf("Unsupported mode\n");
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return 1;
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}
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}
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return 0;
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}
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