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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
130 lines
3 KiB
C
130 lines
3 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define timestamp (gd->arch.tbl)
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#define lastinc (gd->arch.lastinc)
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1<<15) /* Software reset */
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#define GPTCR_FRR (1<<9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
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#define GPTCR_TEN (1) /* Timer enable */
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/*
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* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
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* "tick" is internal timer period
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*/
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/* ~0.4% error - measured with stop-watch on 100s boot-delay */
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, MXC_CLK32);
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return tick;
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}
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static inline unsigned long long us_to_tick(unsigned long long us)
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{
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us = us * MXC_CLK32 + 999999;
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do_div(us, 1000000);
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return us;
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}
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/*
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* nothing really to do with interrupts, just starts up a counter.
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* The 32KHz 32-bit timer overruns in 134217 seconds
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*/
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int timer_init(void)
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{
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int i;
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
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/* setup GP Timer 1 */
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writel(GPTCR_SWR, &gpt->ctrl);
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writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
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for (i = 0; i < 100; i++)
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writel(0, &gpt->ctrl); /* We have no udelay by now */
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writel(0, &gpt->pre); /* prescaler = 1 */
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/* Freerun Mode, 32KHz input */
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writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
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&gpt->ctrl);
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writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
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return 0;
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}
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unsigned long long get_ticks(void)
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{
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struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
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ulong now = readl(&gpt->counter); /* current tick value */
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if (now >= lastinc) {
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/*
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* normal mode (non roll)
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* move stamp forward with absolut diff ticks
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*/
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timestamp += (now - lastinc);
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} else {
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/* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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}
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lastinc = now;
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return timestamp;
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}
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ulong get_timer_masked(void)
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{
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/*
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* get_ticks() returns a long long (64 bit), it wraps in
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* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
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* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
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* 5 * 10^6 days - long enough.
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*/
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return tick_to_time(get_ticks());
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/* delay x useconds AND preserve advance timstamp value */
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void __udelay(unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = us_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return MXC_CLK32;
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}
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